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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- word write enable
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wren_i : in std_ulogic; -- word write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
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clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
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-- CPU state --
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-- CPU state --
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sleep_i : in std_ulogic; -- set if cpu is in sleep mode
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sleep_i : in std_ulogic; -- set if cpu is in sleep mode
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--
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--
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-- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide
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-- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide
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-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>
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-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>
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-- for issueing commands and a <status register> for status information.
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-- for issueing commands and a <status register> for status information.
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--
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--
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal.
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later
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-- If no ACK is generated, the bus access will time out and cause a store bus access fault exception. This exception can also be immediatly
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-- if the module needs additional time; the maximumx latency until an unacknwoledged access will trigger a bus exception is defined via the package's
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-- triggered by setting err_o high for one cycle (only during a valid bus access).
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-- gloabl "bus_timeout_c" constant). If no ACK is generated, the bus access will time out and cause a store bus access fault exception.
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err_o <= '0'; -- not used for this minimal example
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-- Host access: Read and write access to the interface registers + bus transfer acknowledge.
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-- Host access: Read and write access to the interface registers + bus transfer acknowledge.
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-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not
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-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not
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-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.
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-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.
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