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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Custom Functions Subsystem (CFS) >> #
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-- # << NEORV32 - Custom Functions Subsystem (CFS) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # For tightly-coupled custom co-processors. Provides 32x32-bit memory-mapped registers. #
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-- # For tightly-coupled custom co-processors. Provides 32x32-bit memory-mapped registers. This is #
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-- # This is just an "example/illustrating template". Modify this file to implement your custom #
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-- # just an "example/illustration template". Modify this file to implement your own custom design #
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-- # design logic. #
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-- # logic. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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addr <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i; -- full 32-bit word write enable
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wren <= acc_en and wren_i; -- full 32-bit word write enable
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rden <= acc_en and rden_i; -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU
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rden <= acc_en and rden_i; -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU
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-- NOTE: Do not modify the CFS base address or the CFS' occupied address space as this might cause access
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-- collisions with other modules.
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-- CFS Generics ---------------------------------------------------------------------------
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-- CFS Generics ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- In its default version, the CFS provides the configuration generics. single generic:
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-- In its default version, the CFS provides the configuration generics. single generic:
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-- CFS_IN_SIZE configures the size (in bits) of the CFS input conduit cfs_in_i
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-- CFS_IN_SIZE configures the size (in bits) of the CFS input conduit cfs_in_i
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-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
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-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
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-- ...
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-- ...
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-- end if;
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-- end if;
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-- end if;
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-- end if;
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--
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--
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-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the UART) requires the clocks generated by the
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-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the SPI) requires the clocks generated by the
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-- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
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-- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
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-- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated.
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-- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated.
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-- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption.
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-- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption.
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clkgen_en_o <= '0'; -- not used for this minimal example
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clkgen_en_o <= '0'; -- not used for this minimal example
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- The CFS can decide to go into low-power mode (by disabling all switching activity) when the CPU enters sleep mode.
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-- The CFS can decide to go into low-power mode (by disabling all switching activity) when the CPU enters sleep mode.
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-- The sleep_i signal is high when the CPU is in sleep mode. Any interrupt including the CFS's irq_o interrupt request signal
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-- The sleep_i signal is high when the CPU is in sleep mode. Any interrupt including the CFS's irq_o interrupt request signal
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-- will wake up the CPU again.
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-- will wake up the CPU again.
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-- sleep_i
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-- Interrupt ------------------------------------------------------------------------------
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-- Interrupt ------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- The CFS features a single interrupt signal. This interrupt is connected to the CPU's "fast interrupt" channel 1.
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-- The CFS features a single interrupt signal. This interrupt is connected to the CPU's "fast interrupt" channel 1.
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-- Note that this fast interrupt channel is shared with the GPIO pin-change interrupt. Make sure to disable the GPIO's pin-change interrupt
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-- via the according control register if you want to use this interrupt exclusively for the CFS.
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--
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-- The interrupt is single-shot. Setting the irq_o signal high for one cycle will generate an interrupt request.
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-- The interrupt is single-shot. Setting the irq_o signal high for one cycle will generate an interrupt request.
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-- The interrupt is acknowledged by the CPU via the one-shot irq_ack_i signal indicating that the according interrupt handler is starting.
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-- It is recommended to implement some CFS mechanisms (like a register that needs to be written) in order to allow
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-- another generation on an interrupt request (simple acknowledgement).
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irq_o <= '0'; -- not used for this minimal example
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irq_o <= '0'; -- not used for this minimal example
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-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>
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-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>
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-- for issuing commands and a <status register> for status information.
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-- for issuing commands and a <status register> for status information.
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--
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--
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later
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-- if the module needs additional time; the maximum latency until an unacknowledged access will trigger a bus exception is defined via the package's
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-- if the module needs additional time; the maximum latency until an unacknowledged access will trigger a bus exception is defined via the package's
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-- global "bus_timeout_c" constant). If no ACK is generated, the bus access will time out and cause a store bus access fault exception.
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-- global "bus_timeout_c" constant). If no ACK is generated at all, the bus access will time out and cause a bus access fault exception.
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-- Host access: Read and write access to the interface registers + bus transfer acknowledge.
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-- Host access: Read and write access to the interface registers + bus transfer acknowledge.
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-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not
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-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not
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-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.
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-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.
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-- ack_o <= wren; -- use this construct if your CFS is write-only
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-- ack_o <= wren; -- use this construct if your CFS is write-only
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-- ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...)
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-- ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...)
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-- write access --
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-- write access --
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if (wren = '1') then -- word-wide write-access only!
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if (wren = '1') then -- word-wide write-access only!
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case addr is -- make sure to use the internal "addr" signal for the read/write interface
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if (addr = cfs_reg0_addr_c) then -- make sure to use the internal "addr" signal for the read/write interface
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when cfs_reg0_addr_c => cfs_reg_wr(0) <= data_i; -- for example: control register
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cfs_reg_wr(0) <= data_i; -- for example: control register
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when cfs_reg1_addr_c => cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo
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end if;
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when cfs_reg2_addr_c => cfs_reg_wr(2) <= data_i; -- for example: command fifo
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if (addr = cfs_reg1_addr_c) then
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when cfs_reg3_addr_c => cfs_reg_wr(3) <= data_i; -- for example: status register
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cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo
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when others => NULL;
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end if;
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end case;
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if (addr = cfs_reg2_addr_c) then
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cfs_reg_wr(2) <= data_i; -- for example: command fifo
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end if;
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if (addr = cfs_reg3_addr_c) then
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cfs_reg_wr(3) <= data_i; -- for example: status register
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0'); -- the output has to be zero if there is no actual read access
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data_o <= (others => '0'); -- the output has to be zero if there is no actual read access
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if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU
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if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU
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