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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cfs.vhd] - Diff between revs 68 and 69

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Rev 68 Rev 69
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  -- Interrupt ------------------------------------------------------------------------------
 
  -- Interrupt ------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  -- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1.
 
  -- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1.
 
  -- The interrupt is high-level-active. When set, the interrupt appears as "pending" in the CPU's mie register
 
  -- The interrupt is triggered by a one-shot rising edge. After triggering, the interrupt appears as "pending" in the CPU's mie register
 
  -- ready to trigger execution of the according interrupt handler.
 
  -- ready to trigger execution of the according interrupt handler. The interrupt request signal should be triggered
 
  -- Once set, the irq_o signal **has to stay set** until explicitly acknowledged by the CPU
 
  -- whenever an interrupt condition is fulfilled. It is the task of the application to programmer to enable/clear the CFS interrupt
 
  -- (for example by reading/writing from/to a specific CFS interface register address).
 
  -- using the CPU's mie and mip registers when reuqired.
 
 
 
 
 
  irq_o <= '0'; -- not used for this minimal example
 
  irq_o <= '0'; -- not used for this minimal example
 
 
 
 
 
 
 
 
 
  -- Read/Write Access ----------------------------------------------------------------------
 
  -- Read/Write Access ----------------------------------------------------------------------

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