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-- # For tightly-coupled custom co-processors. Provides 32x32-bit memory-mapped registers.         #

-- # Intended for tightly-coupled, application-specific custom co-processors. This module provides #

-- # This is just an "example/illustration template". Modify this file to implement your own       #

-- # 32x 32-bit memory-mapped interface registers, one interrupt request signal and custom IO      #

-- # custom design logic.                                                                          #

-- # conduits for processor-external or chip-external interface.                                   #

-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

-- # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #

  -- These assignments are required to check if the CFS is accessed at all.

  -- This logic is required to handle the CPU accesses.

  wren   <= acc_en and wren_i; -- full 32-bit word write enable

  wren   <= acc_en and wren_i; -- write accesses always write a full 32-bit word

  rden   <= acc_en and rden_i; -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU

  rden   <= acc_en and rden_i; -- read accesses always return a full 32-bit word

  -- In its default version, the CFS provides the configuration generics. single generic:

  -- In it's default version the CFS provides three configuration generics:

  -- CFS_IN_SIZE configures the size (in bits) of the CFS input conduit cfs_in_i

  -- CFS_IN_SIZE  - configures the size (in bits) of the CFS input conduit cfs_in_i

  -- CFS_OUT_SIZE configures the size (in bits) of the CFS output conduit cfs_out_o

  -- CFS_OUT_SIZE - configures the size (in bits) of the CFS output conduit cfs_out_o

  -- CFS_CONFIG is a blank 32-bit generic. It is intended as a "generic conduit" to propagate custom configuration flags from the top entity down to this entiy.

  -- CFS_CONFIG   - is a blank 32-bit generic. It is intended as a "generic conduit" to propagate

  -- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor top entity.

  -- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor's top entity.

  -- These are intended as "conduits" to propagate custom signals this entity <=> processor top entity.

  -- These are intended as "conduits" to propagate custom signals from this module and the processor top entity.

  -- Note that rstn_i can be asserted by an external reset and also by a watchdog-cause reset.

  -- Note that rstn_i can be asserted by a processor-external reset, the on-chip debugger and also by the watchdog.

  -- Most default peripheral devices of the NEORV32 do NOT use a dedicated reset at all. Instead, these units are reset by writing ZERO

  -- Most default peripheral devices of the NEORV32 do NOT use a dedicated hardware reset at all. Instead, these units are

  -- to a specific "control register" located right at the beginning of the device's address space (so this register is cleared at first).

  -- reset by writing ZERO to a specific "control register" located right at the beginning of the device's address space

  -- The crt0 start-up code write ZERO to every single address in the processor's IO space - including the CFS.

  -- (so this register is cleared at first). The crt0 start-up code writes ZERO to every single address in the processor's

  -- Make sure that this clearing does not cause any unintended actions in the CFS.

  -- IO space - including the CFS. Make sure that this initial clearing does not cause any unintended CFS actions.

  -- The processor top unit implements a clock generator providing 8 "derived clocks"

  -- The processor top unit implements a clock generator providing 8 "derived clocks".

  -- The following clock divider rates are available:

  -- The following clock dividers are available:

  -- clkgen_i(clk_div2_c)    -> MAIN_CLK/2

  --  + clkgen_i(clk_div2_c)    -> MAIN_CLK/2

  -- clkgen_i(clk_div4_c)    -> MAIN_CLK/4

  --  + clkgen_i(clk_div4_c)    -> MAIN_CLK/4

  -- clkgen_i(clk_div8_c)    -> MAIN_CLK/8

  --  + clkgen_i(clk_div8_c)    -> MAIN_CLK/8

  -- clkgen_i(clk_div64_c)   -> MAIN_CLK/64

  --  + clkgen_i(clk_div64_c)   -> MAIN_CLK/64

  -- clkgen_i(clk_div128_c)  -> MAIN_CLK/128

  --  + clkgen_i(clk_div128_c)  -> MAIN_CLK/128

  -- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024

  --  + clkgen_i(clk_div1024_c) -> MAIN_CLK/1024

  -- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048

  --  + clkgen_i(clk_div2048_c) -> MAIN_CLK/2048

  -- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096

  --  + clkgen_i(clk_div4096_c) -> MAIN_CLK/4096

  -- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the SPI) requires the clocks generated by the

  -- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the UART) requires the clocks

  -- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.

  -- generated by the clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.

  -- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated.

  -- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might

  -- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption.

  -- still keep the generator activated. Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to

  -- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1.

  -- The CFS features a single interrupt signal, which is connected to the CPU's "fast interrupt" channel 1 (FIRQ1).

  -- The interrupt is triggered by a one-shot rising edge. After triggering, the interrupt appears as "pending" in the CPU's mie register

  -- The interrupt is triggered by a one-cycle high-level. After triggering, the interrupt appears as "pending" in the CPU's

  -- ready to trigger execution of the according interrupt handler. The interrupt request signal should be triggered

  -- mip CSR ready to trigger execution of the according interrupt handler. It is the task of the application to programmer

  -- whenever an interrupt condition is fulfilled. It is the task of the application to programmer to enable/clear the CFS interrupt

  -- to enable/clear the CFS interrupt using the CPU's mie and mip registers when required.

  -- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO

  -- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO modules

  -- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte)

  -- of the NEORV32 can only be written in full word mode (32-bit). Any other write accesses (half-word or byte) will raise

  -- will trigger a store bus access fault exception.

  -- a store bus access fault exception.

  -- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide

  -- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o

  -- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>

  -- signal (or even later if the module needs additional time; exceeding the maximum ACK latency will raise a bus exception).

  -- for issuing commands and a <status register> for status information.

  -- If no ACK is generated at all, the bus access will time out and cause a bus access fault exception.

  -- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later

  -- This module also provides an optional ERROR signal to indicate a faulty access operation (for example when accessing an

  -- if the module needs additional time; the maximum latency until an unacknowledged access will trigger a bus exception is defined via the package's

  -- unused, read-only or "locked" CFS register address). This signal may only be set when the module is actually accessed

  -- global "bus_timeout_c" constant). If no ACK is generated at all, the bus access will time out and cause a bus access fault exception.

  -- and is asserted INSTEAD of the ACK signal. Setting the ERR signal will raise a bus access exception that can be handled

  -- by the application software.

  -- Host access: Read and write access to the interface registers + bus transfer acknowledge.

  -- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not

  err_o <= '0'; -- Tie to zero if not explicitly used.

  -- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.

    if rising_edge(clk_i) then -- synchronous interface for reads and writes

    if rising_edge(clk_i) then -- synchronous interface for read and write accesses

      ack_o <= rden or wren; -- default: required for the CPU to check the CFS is answering a bus read OR write request; all r/w accesses (to any cfs_reg) will succeed

      ack_o <= rden or wren; -- default: required for the CPU to check the CFS is answering a bus read OR write request;

--    ack_o <= rden; -- use this construct if your CFS is read-only

                             -- all r/w accesses (to any cfs_reg) will succeed

      if (wren = '1') then -- word-wide write-access only!

      if (wren = '1') then

          cfs_reg_wr(0) <= data_i; -- for example: control register

          cfs_reg_wr(0) <= data_i; -- physical register, for example: control register

          cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo

          cfs_reg_wr(1) <= data_i; -- physical register, for example: data in/out fifo

          cfs_reg_wr(2) <= data_i; -- for example: command fifo

          cfs_reg_wr(2) <= data_i; -- physical register, for example: command fifo

          cfs_reg_wr(3) <= data_i; -- for example: status register

          cfs_reg_wr(3) <= data_i; -- physical register, for example: status register

      if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU

      if (rden = '1') then -- the read access is always a full 32-bit word wide

  cfs_core: process(cfs_reg_wr)

  cfs_core_logic: process(cfs_reg_wr)

    cfs_reg_rd(0) <= not cfs_reg_wr(0); -- just invert the written value

    cfs_reg_rd(0) <= not cfs_reg_wr(0);

  end process cfs_core;

  end process cfs_core_logic;