| Line 95... |
Line 95... |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_we_o : out std_ulogic; -- write enable
|
bus_we_o : out std_ulogic; -- write enable
|
bus_re_o : out std_ulogic; -- read enable
|
bus_re_o : out std_ulogic; -- read enable
|
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_err_i : in std_ulogic; -- bus transfer error
|
bus_err_i : in std_ulogic; -- bus transfer error
|
|
-- system time input from MTIME --
|
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- external interrupts --
|
-- external interrupts --
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
mtime_irq_i : in std_ulogic -- machine timer interrupt
|
mtime_irq_i : in std_ulogic -- machine timer interrupt
|
);
|
);
|
end neorv32_cpu;
|
end neorv32_cpu;
|
| Line 124... |
Line 127... |
signal ma_load : std_ulogic; -- misaligned load data address
|
signal ma_load : std_ulogic; -- misaligned load data address
|
signal ma_store : std_ulogic; -- misaligned store data address
|
signal ma_store : std_ulogic; -- misaligned store data address
|
signal be_instr : std_ulogic; -- bus error on instruction access
|
signal be_instr : std_ulogic; -- bus error on instruction access
|
signal be_load : std_ulogic; -- bus error on load data access
|
signal be_load : std_ulogic; -- bus error on load data access
|
signal be_store : std_ulogic; -- bus error on store data access
|
signal be_store : std_ulogic; -- bus error on store data access
|
signal bus_exc_ack : std_ulogic; -- bus exception error acknowledge
|
|
signal bus_busy : std_ulogic; -- bus unit is busy
|
signal bus_busy : std_ulogic; -- bus unit is busy
|
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
|
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
|
|
|
| Line 199... |
Line 201... |
csr_wdata_i => alu_res, -- CSR write data
|
csr_wdata_i => alu_res, -- CSR write data
|
csr_rdata_o => csr_rdata, -- CSR read data
|
csr_rdata_o => csr_rdata, -- CSR read data
|
-- external interrupt --
|
-- external interrupt --
|
clic_irq_i => clic_irq_i, -- CLIC interrupt request
|
clic_irq_i => clic_irq_i, -- CLIC interrupt request
|
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
|
-- system time input from MTIME --
|
|
time_i => time_i, -- current system time
|
-- bus access exceptions --
|
-- bus access exceptions --
|
mar_i => mar, -- memory address register
|
mar_i => mar, -- memory address register
|
ma_instr_i => ma_instr, -- misaligned instruction address
|
ma_instr_i => ma_instr, -- misaligned instruction address
|
ma_load_i => ma_load, -- misaligned load data address
|
ma_load_i => ma_load, -- misaligned load data address
|
ma_store_i => ma_store, -- misaligned store data address
|
ma_store_i => ma_store, -- misaligned store data address
|
be_instr_i => be_instr, -- bus error on instruction access
|
be_instr_i => be_instr, -- bus error on instruction access
|
be_load_i => be_load, -- bus error on load data access
|
be_load_i => be_load, -- bus error on load data access
|
be_store_i => be_store, -- bus error on store data access
|
be_store_i => be_store, -- bus error on store data access
|
bus_exc_ack_o => bus_exc_ack, -- bus exception error acknowledge
|
|
bus_busy_i => bus_busy -- bus unit is busy
|
bus_busy_i => bus_busy -- bus unit is busy
|
);
|
);
|
|
|
|
|
-- Register File --------------------------------------------------------------------------
|
-- Register File --------------------------------------------------------------------------
|
| Line 236... |
Line 239... |
|
|
|
|
-- ALU ------------------------------------------------------------------------------------
|
-- ALU ------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_alu_inst: neorv32_cpu_alu
|
neorv32_cpu_alu_inst: neorv32_cpu_alu
|
|
generic map (
|
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement muld/div extension?
|
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
| Line 297... |
Line 303... |
|
|
-- Bus Unit -------------------------------------------------------------------------------
|
-- Bus Unit -------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
generic map (
|
generic map (
|
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
| Line 321... |
Line 328... |
be_instr_o => be_instr, -- bus error on instruction access
|
be_instr_o => be_instr, -- bus error on instruction access
|
be_load_o => be_load, -- bus error on load data access
|
be_load_o => be_load, -- bus error on load data access
|
be_store_o => be_store, -- bus error on store data access
|
be_store_o => be_store, -- bus error on store data access
|
bus_wait_o => bus_wait, -- wait for bus operation to finish
|
bus_wait_o => bus_wait, -- wait for bus operation to finish
|
bus_busy_o => bus_busy, -- bus unit is busy
|
bus_busy_o => bus_busy, -- bus unit is busy
|
exc_ack_i => bus_exc_ack, -- exception controller ACK
|
|
-- bus system --
|
-- bus system --
|
bus_addr_o => bus_addr_o, -- bus access address
|
bus_addr_o => bus_addr_o, -- bus access address
|
bus_rdata_i => bus_rdata_i, -- bus read data
|
bus_rdata_i => bus_rdata_i, -- bus read data
|
bus_wdata_o => bus_wdata_o, -- bus write data
|
bus_wdata_o => bus_wdata_o, -- bus write data
|
bus_ben_o => bus_ben_o, -- byte enable
|
bus_ben_o => bus_ben_o, -- byte enable
|
bus_we_o => bus_we_o, -- write enable
|
bus_we_o => bus_we_o, -- write enable
|
bus_re_o => bus_re_o, -- read enable
|
bus_re_o => bus_re_o, -- read enable
|
|
bus_cancel_o => bus_cancel_o, -- cancel current bus transaction
|
bus_ack_i => bus_ack_i, -- bus transfer acknowledge
|
bus_ack_i => bus_ack_i, -- bus transfer acknowledge
|
bus_err_i => bus_err_i -- bus transfer error
|
bus_err_i => bus_err_i -- bus transfer error
|
);
|
);
|
|
|
|
|
