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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Top Entity >> #
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-- # << NEORV32 - CPU Top Entity >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Top NEORV32 CPU: #
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-- # Top NEORV32 CPU: #
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-- # * neorv32_cpu_alu: Arithemtical/logical unit #
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-- # * neorv32_cpu_alu: Arithemtic/logic unit #
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-- # * neorv32_cpu_ctrl: CPU control and CSR system #
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-- # * neorv32_cpu_ctrl: CPU control and CSR system #
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-- # * neorv32_cpu_decompressor: Compressed instructions decoder #
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-- # * neorv32_cpu_decompressor: Compressed instructions decoder #
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-- # * neorv32_cpu_bus: Memory/IO bus interface unit #
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-- # * neorv32_cpu_bus: Instruction and data bus interface unit #
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-- # * neorv32_cpu_cp_muldiv: MULDIV co-processor #
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-- # * neorv32_cpu_cp_muldiv: MULDIV co-processor #
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-- # * neorv32_cpu_regfile: Data register file #
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-- # * neorv32_cpu_regfile: Data register file #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu is
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entity neorv32_cpu is
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generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
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-- Memory configuration: Data memory --
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MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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-- Memory configuration: External memory interface --
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-- Memory configuration: External memory interface --
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MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
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-- Processor peripherals --
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IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- bus interface --
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-- instruction bus interface --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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i_bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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-- data bus interface --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- external interrupts --
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-- external interrupts --
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msw_irq_i : in std_ulogic; -- software interrupt
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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);
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);
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end neorv32_cpu;
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end neorv32_cpu;
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
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signal bus_wait : std_ulogic; -- wait for bus to finish operation
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signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
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signal bus_d_wait : std_ulogic; -- wait for current bus data access
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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signal ma_instr : std_ulogic; -- misaligned instruction address
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signal ma_instr : std_ulogic; -- misaligned instruction address
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signal ma_load : std_ulogic; -- misaligned load data address
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signal ma_load : std_ulogic; -- misaligned load data address
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signal ma_store : std_ulogic; -- misaligned store data address
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signal ma_store : std_ulogic; -- misaligned store data address
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal bus_busy : std_ulogic; -- bus unit is busy
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
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-- co-processor interface --
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-- co-processor interface --
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-- Control Unit ---------------------------------------------------------------------------
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-- Control Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_control_inst: neorv32_cpu_control
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neorv32_cpu_control_inst: neorv32_cpu_control
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generic map (
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generic map (
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-- General --
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-- General --
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CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
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HART_ID => HART_ID, -- custom hardware thread ID
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BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
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CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
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CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei -- implement instruction stream sync.?
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE => MEM_ISPACE_BASE, -- base address of instruction memory space
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MEM_ISPACE_SIZE => MEM_ISPACE_SIZE, -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM
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-- Memory configuration: Data memory --
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MEM_DSPACE_BASE => MEM_DSPACE_BASE, -- base address of data memory space
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MEM_DSPACE_SIZE => MEM_DSPACE_SIZE, -- total size of data memory space in byte
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MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
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-- Memory configuration: External memory interface --
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MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface?
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-- Processor peripherals --
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IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)?
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IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
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IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
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IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
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IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
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)
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)
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port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_o => ctrl, -- main control bus
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ctrl_o => ctrl, -- main control bus
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-- status input --
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-- status input --
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alu_wait_i => alu_wait, -- wait for ALU
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alu_wait_i => alu_wait, -- wait for ALU
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bus_wait_i => bus_wait, -- wait for bus
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bus_i_wait_i => bus_i_wait, -- wait for bus
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bus_d_wait_i => bus_d_wait, -- wait for bus
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-- data input --
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-- data input --
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instr_i => instr, -- instruction
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instr_i => instr, -- instruction
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cmp_i => alu_cmp, -- comparator status
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cmp_i => alu_cmp, -- comparator status
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alu_add_i => alu_add, -- ALU.add result
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alu_add_i => alu_add, -- ALU.add result
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-- data output --
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-- data output --
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next_pc_o => next_pc, -- next PC (corresponding to current instruction)
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next_pc_o => next_pc, -- next PC (corresponding to current instruction)
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-- csr interface --
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-- csr interface --
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csr_wdata_i => alu_res, -- CSR write data
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csr_wdata_i => alu_res, -- CSR write data
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csr_rdata_o => csr_rdata, -- CSR read data
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csr_rdata_o => csr_rdata, -- CSR read data
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-- external interrupt --
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-- external interrupt --
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msw_irq_i => msw_irq_i, -- software interrupt
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clic_irq_i => clic_irq_i, -- CLIC interrupt request
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clic_irq_i => clic_irq_i, -- CLIC interrupt request
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i => time_i, -- current system time
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time_i => time_i, -- current system time
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-- bus access exceptions --
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-- bus access exceptions --
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Line 176... |
ma_instr_i => ma_instr, -- misaligned instruction address
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ma_instr_i => ma_instr, -- misaligned instruction address
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ma_load_i => ma_load, -- misaligned load data address
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ma_load_i => ma_load, -- misaligned load data address
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ma_store_i => ma_store, -- misaligned store data address
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ma_store_i => ma_store, -- misaligned store data address
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be_instr_i => be_instr, -- bus error on instruction access
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be_instr_i => be_instr, -- bus error on instruction access
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be_load_i => be_load, -- bus error on load data access
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be_load_i => be_load, -- bus error on load data access
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be_store_i => be_store, -- bus error on store data access
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be_store_i => be_store -- bus error on store data access
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bus_busy_i => bus_busy -- bus unit is busy
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);
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);
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-- Register File --------------------------------------------------------------------------
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-- Register File --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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Line 264... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cp1_data <= (others => '0');
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cp1_data <= (others => '0');
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cp1_valid <= '0';
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cp1_valid <= '0';
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-- Bus Unit -------------------------------------------------------------------------------
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-- Bus Interface Unit ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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generic map (
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generic map (
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
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MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
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| Line 311... |
Line 276... |
port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- data input --
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-- cpu instruction fetch interface --
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wdata_i => rs2, -- write data
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fetch_pc_i => fetch_pc, -- PC for instruction fetch
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pc_i => fetch_pc, -- current PC for instruction fetch
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alu_i => alu_res, -- ALU result
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-- data output --
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instr_o => instr, -- instruction
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instr_o => instr, -- instruction
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i_wait_o => bus_i_wait, -- wait for fetch to complete
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--
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ma_instr_o => ma_instr, -- misaligned instruction address
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be_instr_o => be_instr, -- bus error on instruction access
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-- cpu data access interface --
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addr_i => alu_add, -- ALU.add result -> access address
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wdata_i => rs2, -- write data
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rdata_o => rdata, -- read data
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rdata_o => rdata, -- read data
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-- status --
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mar_o => mar, -- current memory address register
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mar_o => mar, -- current memory address register
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ma_instr_o => ma_instr, -- misaligned instruction address
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d_wait_o => bus_d_wait, -- wait for access to complete
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--
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ma_load_o => ma_load, -- misaligned load data address
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ma_load_o => ma_load, -- misaligned load data address
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ma_store_o => ma_store, -- misaligned store data address
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ma_store_o => ma_store, -- misaligned store data address
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be_instr_o => be_instr, -- bus error on instruction access
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be_load_o => be_load, -- bus error on load data access
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be_load_o => be_load, -- bus error on load data access
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be_store_o => be_store, -- bus error on store data access
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be_store_o => be_store, -- bus error on store data access
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bus_wait_o => bus_wait, -- wait for bus operation to finish
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-- instruction bus --
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bus_busy_o => bus_busy, -- bus unit is busy
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i_bus_addr_o => i_bus_addr_o, -- bus access address
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-- bus system --
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i_bus_rdata_i => i_bus_rdata_i, -- bus read data
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bus_addr_o => bus_addr_o, -- bus access address
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i_bus_wdata_o => i_bus_wdata_o, -- bus write data
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bus_rdata_i => bus_rdata_i, -- bus read data
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
bus_wdata_o => bus_wdata_o, -- bus write data
|
i_bus_we_o => i_bus_we_o, -- write enable
|
bus_ben_o => bus_ben_o, -- byte enable
|
i_bus_re_o => i_bus_re_o, -- read enable
|
bus_we_o => bus_we_o, -- write enable
|
i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
|
bus_re_o => bus_re_o, -- read enable
|
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
|
bus_cancel_o => bus_cancel_o, -- cancel current bus transaction
|
i_bus_err_i => i_bus_err_i, -- bus transfer error
|
bus_ack_i => bus_ack_i, -- bus transfer acknowledge
|
i_bus_fence_o => i_bus_fence_o, -- fence operation
|
bus_err_i => bus_err_i -- bus transfer error
|
-- data bus --
|
|
d_bus_addr_o => d_bus_addr_o, -- bus access address
|
|
d_bus_rdata_i => d_bus_rdata_i, -- bus read data
|
|
d_bus_wdata_o => d_bus_wdata_o, -- bus write data
|
|
d_bus_ben_o => d_bus_ben_o, -- byte enable
|
|
d_bus_we_o => d_bus_we_o, -- write enable
|
|
d_bus_re_o => d_bus_re_o, -- read enable
|
|
d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
|
|
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
|
|
d_bus_err_i => d_bus_err_i, -- bus transfer error
|
|
d_bus_fence_o => d_bus_fence_o -- fence operation
|
);
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);
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|
|
|
|
end neorv32_cpu_rtl;
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end neorv32_cpu_rtl;
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No newline at end of file
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No newline at end of file
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