| Line 56... |
Line 56... |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
|
-- Physical Memory Protection (PMP) --
|
|
PMP_USE : boolean := false; -- implement PMP?
|
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
|
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PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
-- Bus Interface --
|
-- Bus Interface --
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
|
port (
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-- global control --
|
-- global control --
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| Line 128... |
Line 133... |
|
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-- co-processor interface --
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-- co-processor interface --
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_valid, cp1_valid : std_ulogic;
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signal cp0_valid, cp1_valid : std_ulogic;
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|
|
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-- pmp interface --
|
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signal pmp_addr : pmp_addr_if_t;
|
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signal pmp_maddr : pmp_addr_if_t;
|
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signal pmp_ctrl : pmp_ctrl_if_t;
|
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signal priv_mode : std_ulogic_vector(1 downto 0); -- current CPU privilege level
|
|
|
|
begin
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|
|
|
-- Sanity Checks --------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
sanity_check: process(clk_i)
|
begin
|
begin
|
|
if rising_edge(clk_i) then
|
|
-- CSR system --
|
|
if (CPU_EXTENSION_RISCV_Zicsr = false) then
|
|
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
|
|
end if;
|
|
-- U-extension requires Zicsr extension --
|
|
if (CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true) then
|
|
assert false report "NEORV32 CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr = true." severity error;
|
|
end if;
|
|
-- PMP requires Zicsr extension --
|
|
if (CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_USE = true) then
|
|
assert false report "NEORV32 CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr = true." severity error;
|
|
end if;
|
|
-- performance counters requires Zicsr extension --
|
|
if (CPU_EXTENSION_RISCV_Zicsr = false) and (CSR_COUNTERS_USE = true) then
|
|
assert false report "NEORV32 CONFIG ERROR! Performance counter CSRs require CPU_EXTENSION_RISCV_Zicsr = true." severity error;
|
|
end if;
|
|
-- PMP regions --
|
|
if (PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true) then
|
|
assert false report "NEORV32 CONFIG ERROR! Number of PMP regions out of valid range." severity error;
|
|
end if;
|
|
-- PMP granulartiy --
|
|
if ((PMP_GRANULARITY <= 1) or (PMP_GRANULARITY > 31)) and (PMP_USE = true) then
|
|
assert false report "NEORV32 CONFIG ERROR! Invalid PMP grnaulartiy (1 < G < 32)." severity error;
|
|
end if;
|
|
end if;
|
|
end process sanity_check;
|
|
|
-- Control Unit ---------------------------------------------------------------------------
|
-- Control Unit ---------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_control_inst: neorv32_cpu_control
|
neorv32_cpu_control_inst: neorv32_cpu_control
|
generic map (
|
generic map (
|
| Line 142... |
Line 185... |
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
|
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
|
-- Physical memory protection (PMP) --
|
|
PMP_USE => PMP_USE, -- implement physical memory protection?
|
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (1..4)
|
|
PMP_GRANULARITY => PMP_GRANULARITY -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
| Line 174... |
Line 222... |
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i => firq_i,
|
firq_i => firq_i,
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i => time_i, -- current system time
|
time_i => time_i, -- current system time
|
|
-- physical memory protection --
|
|
pmp_addr_o => pmp_addr, -- addresses
|
|
pmp_maddr_i => pmp_maddr, -- masked addresses
|
|
pmp_ctrl_o => pmp_ctrl, -- configs
|
|
priv_mode_o => priv_mode, -- current CPU privilege level
|
-- bus access exceptions --
|
-- bus access exceptions --
|
mar_i => mar, -- memory address register
|
mar_i => mar, -- memory address register
|
ma_instr_i => ma_instr, -- misaligned instruction address
|
ma_instr_i => ma_instr, -- misaligned instruction address
|
ma_load_i => ma_load, -- misaligned load data address
|
ma_load_i => ma_load, -- misaligned load data address
|
ma_store_i => ma_store, -- misaligned store data address
|
ma_store_i => ma_store, -- misaligned store data address
|
| Line 274... |
Line 327... |
-- Bus Interface Unit ---------------------------------------------------------------------
|
-- Bus Interface Unit ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
generic map (
|
generic map (
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
BUS_TIMEOUT => BUS_TIMEOUT -- cycles after which a valid bus access will timeout
|
BUS_TIMEOUT => BUS_TIMEOUT, -- cycles after which a valid bus access will timeout
|
|
-- Physical memory protection (PMP) --
|
|
PMP_USE => PMP_USE, -- implement physical memory protection?
|
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (1..4)
|
|
PMP_GRANULARITY => PMP_GRANULARITY -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
| Line 299... |
Line 356... |
--
|
--
|
ma_load_o => ma_load, -- misaligned load data address
|
ma_load_o => ma_load, -- misaligned load data address
|
ma_store_o => ma_store, -- misaligned store data address
|
ma_store_o => ma_store, -- misaligned store data address
|
be_load_o => be_load, -- bus error on load data access
|
be_load_o => be_load, -- bus error on load data access
|
be_store_o => be_store, -- bus error on store data access
|
be_store_o => be_store, -- bus error on store data access
|
|
-- physical memory protection --
|
|
pmp_addr_i => pmp_addr, -- addresses
|
|
pmp_maddr_o => pmp_maddr, -- masked addresses
|
|
pmp_ctrl_i => pmp_ctrl, -- configs
|
|
priv_mode_i => priv_mode, -- current CPU privilege level
|
-- instruction bus --
|
-- instruction bus --
|
i_bus_addr_o => i_bus_addr_o, -- bus access address
|
i_bus_addr_o => i_bus_addr_o, -- bus access address
|
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
|
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
|
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
|
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
