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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Top Entity >> #
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-- # << NEORV32 - CPU Top Entity >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # NEORV32 CPU: #
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-- # NEORV32 CPU: #
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-- # * neorv32_cpu.vhd : CPU top entity #
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-- # * neorv32_cpu.vhd - CPU top entity #
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-- # * neorv32_cpu_alu.vhd : Arithmetic/logic unit #
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-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
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-- # * neorv32_cpu_bus.vhd : Instruction and data bus interface unit #
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-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
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-- # * neorv32_cpu_cp_muldiv.vhd : MULDIV co-processor #
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-- # * neorv32_cpu_cp_muldiv.vhd - MULDIV co-processor #
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-- # * neorv32_cpu_ctrl.vhd : CPU control and CSR system #
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-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system #
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-- # * neorv32_cpu_decompressor.vhd : Compressed instructions decoder #
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-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder #
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-- # * neorv32_cpu_regfile.vhd : Data register file #
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-- # * neorv32_cpu_regfile.vhd - Data register file #
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-- # #
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-- # #
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-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf #
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-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal alu_opb : std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand b
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
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signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
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signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
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signal bus_d_wait : std_ulogic; -- wait for current bus data access
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signal bus_d_wait : std_ulogic; -- wait for current bus data access
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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| Line 133... |
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next to-be-executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next to-be-executed instruction)
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-- co-processor interface --
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-- co-processor interface --
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_data, cp1_data, cp2_data, cp3_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_valid, cp1_valid : std_ulogic;
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signal cp0_valid, cp1_valid, cp2_valid, cp3_valid : std_ulogic;
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signal cp0_start, cp1_start : std_ulogic;
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signal cp0_start, cp1_start, cp2_start, cp3_start : std_ulogic;
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-- pmp interface --
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-- pmp interface --
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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signal priv_mode : std_ulogic_vector(1 downto 0); -- current CPU privilege level
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- CSR system --
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-- CSR system --
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assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
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assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
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-- U-extension requires Zicsr extension --
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-- U-extension requires Zicsr extension --
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
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-- PMP requires Zicsr extension --
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-- PMP requires Zicsr extension --
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
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-- PMP regions --
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-- PMP regions --
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assert not ((PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range." severity error;
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assert not ((PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range." severity error;
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-- PMP granulartiy --
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-- PMP granulartiy --
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assert not (((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < G < 33)." severity error;
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assert not (((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < PMP_GRANULARITY < 33)." severity error;
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-- Control Unit ---------------------------------------------------------------------------
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-- Control Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_control_inst: neorv32_cpu_control
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neorv32_cpu_control_inst: neorv32_cpu_control
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| Line 189... |
Line 190... |
bus_i_wait_i => bus_i_wait, -- wait for bus
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bus_i_wait_i => bus_i_wait, -- wait for bus
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bus_d_wait_i => bus_d_wait, -- wait for bus
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bus_d_wait_i => bus_d_wait, -- wait for bus
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-- data input --
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-- data input --
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instr_i => instr, -- instruction
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instr_i => instr, -- instruction
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cmp_i => alu_cmp, -- comparator status
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cmp_i => alu_cmp, -- comparator status
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alu_res_i => alu_res, -- ALU processing result
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alu_add_i => alu_add, -- ALU address result
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rs1_i => rs1, -- rf source 1
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-- data output --
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-- data output --
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imm_o => imm, -- immediate
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imm_o => imm, -- immediate
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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next_pc_o => next_pc, -- next PC (corresponding to current instruction
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next_pc_o => next_pc, -- next PC (corresponding to current instruction
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| Line 207... |
Line 209... |
-- system time input from MTIME --
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-- system time input from MTIME --
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time_i => time_i, -- current system time
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time_i => time_i, -- current system time
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-- physical memory protection --
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-- physical memory protection --
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pmp_addr_o => pmp_addr, -- addresses
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pmp_addr_o => pmp_addr, -- addresses
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pmp_ctrl_o => pmp_ctrl, -- configs
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pmp_ctrl_o => pmp_ctrl, -- configs
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priv_mode_o => priv_mode, -- current CPU privilege level
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-- bus access exceptions --
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-- bus access exceptions --
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mar_i => mar, -- memory address register
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mar_i => mar, -- memory address register
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ma_instr_i => ma_instr, -- misaligned instruction address
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ma_instr_i => ma_instr, -- misaligned instruction address
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ma_load_i => ma_load, -- misaligned load data address
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ma_load_i => ma_load, -- misaligned load data address
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ma_store_i => ma_store, -- misaligned store data address
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ma_store_i => ma_store, -- misaligned store data address
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| Line 260... |
Line 261... |
pc2_i => curr_pc, -- delayed PC
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pc2_i => curr_pc, -- delayed PC
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imm_i => imm, -- immediate
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imm_i => imm, -- immediate
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-- data output --
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-- data output --
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cmp_o => alu_cmp, -- comparator status
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cmp_o => alu_cmp, -- comparator status
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res_o => alu_res, -- ALU result
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res_o => alu_res, -- ALU result
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add_o => alu_add, -- address computation result
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opb_o => alu_opb, -- ALU operand B
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-- co-processor interface --
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-- co-processor interface --
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cp0_start_o => cp0_start, -- trigger co-processor 0
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cp0_start_o => cp0_start, -- trigger co-processor 0
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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cp1_start_o => cp1_start, -- trigger co-processor 1
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cp1_start_o => cp1_start, -- trigger co-processor 1
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cp1_data_i => cp1_data, -- co-processor 1 result
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cp1_data_i => cp1_data, -- co-processor 1 result
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cp1_valid_i => cp1_valid, -- co-processor 1 result valid
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cp1_valid_i => cp1_valid, -- co-processor 1 result valid
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cp2_start_o => cp2_start, -- trigger co-processor 2
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cp2_data_i => cp2_data, -- co-processor 2 result
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cp2_valid_i => cp2_valid, -- co-processor 2 result valid
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cp3_start_o => cp3_start, -- trigger co-processor 3
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cp3_data_i => cp3_data, -- co-processor 3 result
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cp3_valid_i => cp3_valid, -- co-processor 3 result valid
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-- status --
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-- status --
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wait_o => alu_wait -- busy due to iterative processing units
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wait_o => alu_wait -- busy due to iterative processing units
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);
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);
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| Line 285... |
Line 294... |
port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- data input --
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start_i => cp0_start, -- trigger operation
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start_i => cp0_start, -- trigger operation
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-- data input --
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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-- result and status --
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-- result and status --
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res_o => cp0_data, -- operation result
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res_o => cp0_data, -- operation result
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valid_o => cp0_valid -- data output valid
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valid_o => cp0_valid -- data output valid
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| Line 302... |
Line 311... |
cp0_data <= (others => '0');
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cp0_data <= (others => '0');
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cp0_valid <= '0';
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cp0_valid <= '0';
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end generate;
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end generate;
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-- Co-Processor 1: Not Implemented Yet ----------------------------------------------------
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-- Co-Processor 1: Not implemented yet ----------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- control: ctrl cp1_start
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-- inputs: rs1 rs2 alu_cmp alu_opb
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cp1_data <= (others => '0');
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cp1_data <= (others => '0');
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cp1_valid <= '0';
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cp1_valid <= '0';
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-- Co-Processor 2: Not implemented yet ----------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- control: ctrl cp2_start
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-- inputs: rs1 rs2 alu_cmp alu_opb
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cp2_data <= (others => '0');
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cp2_valid <= '0';
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-- Co-Processor 3: Not implemented yet ----------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- control: ctrl cp3_start
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-- inputs: rs1 rs2 alu_cmp alu_opb
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cp3_data <= (others => '0');
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cp3_valid <= '0';
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-- Bus Interface Unit ---------------------------------------------------------------------
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-- Bus Interface Unit ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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generic map (
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generic map (
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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| Line 321... |
Line 348... |
PMP_GRANULARITY => PMP_GRANULARITY -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
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PMP_GRANULARITY => PMP_GRANULARITY -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
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)
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)
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port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- cpu instruction fetch interface --
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-- cpu instruction fetch interface --
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fetch_pc_i => fetch_pc, -- PC for instruction fetch
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fetch_pc_i => fetch_pc, -- PC for instruction fetch
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instr_o => instr, -- instruction
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instr_o => instr, -- instruction
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i_wait_o => bus_i_wait, -- wait for fetch to complete
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i_wait_o => bus_i_wait, -- wait for fetch to complete
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| Line 344... |
Line 370... |
be_load_o => be_load, -- bus error on load data access
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be_load_o => be_load, -- bus error on load data access
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be_store_o => be_store, -- bus error on store data access
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be_store_o => be_store, -- bus error on store data access
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-- physical memory protection --
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-- physical memory protection --
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pmp_addr_i => pmp_addr, -- addresses
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pmp_addr_i => pmp_addr, -- addresses
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pmp_ctrl_i => pmp_ctrl, -- configs
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pmp_ctrl_i => pmp_ctrl, -- configs
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priv_mode_i => priv_mode, -- current CPU privilege level
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-- instruction bus --
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-- instruction bus --
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i_bus_addr_o => i_bus_addr_o, -- bus access address
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i_bus_addr_o => i_bus_addr_o, -- bus access address
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i_bus_rdata_i => i_bus_rdata_i, -- bus read data
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i_bus_rdata_i => i_bus_rdata_i, -- bus read data
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i_bus_wdata_o => i_bus_wdata_o, -- bus write data
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i_bus_wdata_o => i_bus_wdata_o, -- bus write data
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i_bus_ben_o => i_bus_ben_o, -- byte enable
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i_bus_ben_o => i_bus_ben_o, -- byte enable
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| Line 370... |
Line 395... |
d_bus_err_i => d_bus_err_i, -- bus transfer error
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d_bus_err_i => d_bus_err_i, -- bus transfer error
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d_bus_fence_o => d_bus_fence_o -- fence operation
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d_bus_fence_o => d_bus_fence_o -- fence operation
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);
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);
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-- current privilege level --
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-- current privilege level --
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i_bus_priv_o <= priv_mode;
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i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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d_bus_priv_o <= priv_mode;
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d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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end neorv32_cpu_rtl;
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end neorv32_cpu_rtl;
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No newline at end of file
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No newline at end of file
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