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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu is
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entity neorv32_cpu is
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generic (
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generic (
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-- General --
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-- General --
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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signal be_store : std_ulogic; -- bus error on store data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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-- co-processor interface --
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-- co-processor interface --
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signal cp0_data, cp1_data, cp2_data, cp3_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
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signal cp0_valid, cp1_valid, cp2_valid, cp3_valid : std_ulogic;
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signal cp_valid : std_ulogic_vector(7 downto 0); -- co-processor i done
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signal cp0_start, cp1_start, cp2_start, cp3_start : std_ulogic;
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signal cp_result : cp_data_if_t; -- co-processor result
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-- pmp interface --
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-- pmp interface --
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- data input --
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-- data input --
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mem_i => rdata, -- memory read data
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mem_i => rdata, -- memory read data
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alu_i => alu_res, -- ALU result
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alu_i => alu_res, -- ALU result
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csr_i => csr_rdata, -- CSR read data
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-- data output --
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-- data output --
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rs1_o => rs1, -- operand 1
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rs1_o => rs1, -- operand 1
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rs2_o => rs2, -- operand 2
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rs2_o => rs2, -- operand 2
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cmp_o => comparator -- comparator status
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cmp_o => comparator -- comparator status
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);
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);
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imm_i => imm, -- immediate
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imm_i => imm, -- immediate
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-- data output --
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-- data output --
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res_o => alu_res, -- ALU result
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res_o => alu_res, -- ALU result
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add_o => alu_add, -- address computation result
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add_o => alu_add, -- address computation result
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-- co-processor interface --
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-- co-processor interface --
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cp0_start_o => cp0_start, -- trigger co-processor 0
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cp_start_o => cp_start, -- trigger co-processor i
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp_valid_i => cp_valid, -- co-processor i done
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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cp_result_i => cp_result, -- co-processor result
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cp1_start_o => cp1_start, -- trigger co-processor 1
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cp1_data_i => cp1_data, -- co-processor 1 result
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cp1_valid_i => cp1_valid, -- co-processor 1 result valid
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cp2_start_o => cp2_start, -- trigger co-processor 2
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cp2_data_i => cp2_data, -- co-processor 2 result
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cp2_valid_i => cp2_valid, -- co-processor 2 result valid
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cp3_start_o => cp3_start, -- trigger co-processor 3
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cp3_data_i => cp3_data, -- co-processor 3 result
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cp3_valid_i => cp3_valid, -- co-processor 3 result valid
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-- status --
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-- status --
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wait_o => alu_wait -- busy due to iterative processing units
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wait_o => alu_wait -- busy due to iterative processing units
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);
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);
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port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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start_i => cp0_start, -- trigger operation
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start_i => cp_start(0), -- trigger operation
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-- data input --
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-- data input --
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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-- result and status --
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-- result and status --
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res_o => cp0_data, -- operation result
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res_o => cp_result(0), -- operation result
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valid_o => cp0_valid -- data output valid
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valid_o => cp_valid(0) -- data output valid
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);
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);
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end generate;
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end generate;
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neorv32_cpu_cp_muldiv_inst_false:
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neorv32_cpu_cp_muldiv_inst_false:
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if (CPU_EXTENSION_RISCV_M = false) generate
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if (CPU_EXTENSION_RISCV_M = false) generate
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cp0_data <= (others => '0');
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cp_result(0) <= (others => '0');
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cp0_valid <= cp0_start; -- to make sure CPU does not get stalled if there is an accidental access
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cp_valid(0) <= cp_start(0); -- to make sure CPU does not get stalled if there is an accidental access
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end generate;
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end generate;
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-- Co-Processor 1: Atomic Memory Access ('A' Extension) -----------------------------------
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-- Co-Processor 1: Atomic Memory Access ('A' Extension) -----------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- "pseudo" co-processor for atomic operations
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-- "pseudo" co-processor for atomic operations
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-- used to get the result of a store-conditional operation into the data path
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-- required to get the result of a store-conditional operation into the data path
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atomic_op_cp: process(clk_i)
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atomic_op_cp: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (cp1_start = '1') then
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if (cp_start(1) = '1') then
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atomic_sc_res <= not ctrl(ctrl_bus_lock_c);
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atomic_sc_res <= not ctrl(ctrl_bus_lock_c);
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else
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else
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atomic_sc_res <= '0';
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atomic_sc_res <= '0';
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end if;
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end if;
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end if;
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end if;
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end process atomic_op_cp;
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end process atomic_op_cp;
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-- CP result --
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-- CP result --
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cp1_data(data_width_c-1 downto 1) <= (others => '0');
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cp_result(1)(data_width_c-1 downto 1) <= (others => '0');
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cp1_data(0) <= atomic_sc_res when (CPU_EXTENSION_RISCV_A = true) else '0';
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cp_result(1)(0) <= atomic_sc_res when (CPU_EXTENSION_RISCV_A = true) else '0';
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cp1_valid <= cp1_start; -- always assigned even if A is disabled to make sure CPU does not get stalled if there is an accidental access
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cp_valid(1) <= cp_start(1); -- always assigned even if A extension is disabled to make sure CPU does not get stalled if there is an accidental access
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-- Co-Processor 2: Bit Manipulation ('B' Extension) ---------------------------------------
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-- Co-Processor 2: Bit Manipulation ('B' Extension) ---------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_cp_bitmanip_inst_true:
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neorv32_cpu_cp_bitmanip_inst_true:
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port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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start_i => cp2_start, -- trigger operation
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start_i => cp_start(2), -- trigger operation
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-- data input --
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-- data input --
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cmp_i => comparator, -- comparator status
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cmp_i => comparator, -- comparator status
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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-- result and status --
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-- result and status --
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res_o => cp2_data, -- operation result
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res_o => cp_result(2), -- operation result
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valid_o => cp2_valid -- data output valid
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valid_o => cp_valid(2) -- data output valid
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);
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);
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end generate;
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end generate;
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neorv32_cpu_cp_bitmanip_inst_false:
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neorv32_cpu_cp_bitmanip_inst_false:
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if (CPU_EXTENSION_RISCV_B = false) generate
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if (CPU_EXTENSION_RISCV_B = false) generate
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cp2_data <= (others => '0');
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cp_result(2) <= (others => '0');
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cp2_valid <= cp2_start; -- to make sure CPU does not get stalled if there is an accidental access
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cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
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end generate;
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end generate;
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-- Co-Processor 3: Not implemented --------------------------------------------------------
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-- Co-Processor 3: CSR (Read) Access ('Zicsr' Extension) ----------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cp3_data <= (others => '0');
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-- "pseudo" co-processor for CSR *read* access operations
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cp3_valid <= cp3_start; -- to make sure CPU does not get stalled if there is an accidental access
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-- required to get the CSR read data into the data path
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cp_result(3) <= csr_rdata when (CPU_EXTENSION_RISCV_Zicsr = true) else (others => '0');
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cp_valid(3) <= cp_start(3); -- always assigned even if Zicsr extension is disabled to make sure CPU does not get stalled if there is an accidental access
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-- Co-Processor 4..7: Not Implemented Yet -------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cp_result(4) <= (others => '0');
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cp_valid(4) <= '0';
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--
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cp_result(5) <= (others => '0');
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cp_valid(5) <= '0';
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--
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cp_result(6) <= (others => '0');
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cp_valid(6) <= '0';
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--
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cp_result(7) <= (others => '0');
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cp_valid(7) <= '0';
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-- Bus Interface Unit ---------------------------------------------------------------------
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-- Bus Interface Unit ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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