| Line 3... |
Line 3... |
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # NEORV32 CPU: #
|
-- # NEORV32 CPU: #
|
-- # * neorv32_cpu.vhd - CPU top entity #
|
-- # * neorv32_cpu.vhd - CPU top entity #
|
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
|
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
|
-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
|
-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
|
-- # * neorv32_cpu_cp_muldiv.vhd - MULDIV co-processor #
|
-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor ('B') #
|
|
-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor ('F') #
|
|
-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor ('M') #
|
-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system #
|
-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system #
|
-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder #
|
-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder #
|
-- # * neorv32_cpu_regfile.vhd - Data register file #
|
-- # * neorv32_cpu_regfile.vhd - Data register file #
|
-- # * neorv32_package.vhd - Main CPU/processor package file #
|
-- # * neorv32_package.vhd - Main CPU/processor package file #
|
-- # #
|
-- # #
|
| Line 60... |
Line 62... |
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
|
CPU_EXTENSION_RISCV_F : boolean := false; -- implement 32-bit floating-point extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
| Line 126... |
Line 129... |
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
|
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
|
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
|
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
|
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
|
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
|
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
|
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
|
signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
|
signal mem_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory write-data
|
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
|
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
|
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
|
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
|
signal bus_d_wait : std_ulogic; -- wait for current bus data access
|
signal bus_d_wait : std_ulogic; -- wait for current bus data access
|
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
| Line 140... |
Line 144... |
signal be_instr : std_ulogic; -- bus error on instruction access
|
signal be_instr : std_ulogic; -- bus error on instruction access
|
signal be_load : std_ulogic; -- bus error on load data access
|
signal be_load : std_ulogic; -- bus error on load data access
|
signal be_store : std_ulogic; -- bus error on store data access
|
signal be_store : std_ulogic; -- bus error on store data access
|
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
|
signal fpu_mem_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory write-data form FPU
|
|
signal fpu_rm : std_ulogic_vector(2 downto 0); -- FPU rounding mode
|
|
signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
|
|
|
-- co-processor interface --
|
-- co-processor interface --
|
signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
|
signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
|
signal cp_valid : std_ulogic_vector(7 downto 0); -- co-processor i done
|
signal cp_valid : std_ulogic_vector(7 downto 0); -- co-processor i done
|
signal cp_result : cp_data_if_t; -- co-processor result
|
signal cp_result : cp_data_if_t; -- co-processor result
|
| Line 172... |
Line 179... |
-- Instruction prefetch buffer size --
|
-- Instruction prefetch buffer size --
|
assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
|
assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
|
-- A extension - only lr.w and sc.w are supported yet --
|
-- A extension - only lr.w and sc.w are supported yet --
|
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity warning;
|
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity warning;
|
|
|
-- Bit manipulation notifier --
|
-- FIXME: Bit manipulation warning --
|
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still highly experimental (not ratified yet)." severity warning;
|
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still HIGHLY EXPERIMENTAL (and spec. is not ratified yet)." severity warning;
|
|
|
|
-- FIXME: Floating-point extension warning --
|
|
assert not (CPU_EXTENSION_RISCV_F = true) report "NEORV32 CPU CONFIG WARNING! 32-bit floating-point extension (F) is WORK-IN-PROGRESS and NOT OPERATIONAL yet." severity warning;
|
|
|
-- PMP regions check --
|
-- PMP regions check --
|
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error;
|
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error;
|
-- PMP granulartiy --
|
-- PMP granulartiy --
|
assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be a power of two." severity error;
|
assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be a power of two." severity error;
|
| Line 203... |
Line 213... |
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
|
CPU_EXTENSION_RISCV_F => CPU_EXTENSION_RISCV_F, -- implement 32-bit floating-point extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
| Line 232... |
Line 243... |
-- data output --
|
-- data output --
|
imm_o => imm, -- immediate
|
imm_o => imm, -- immediate
|
fetch_pc_o => fetch_pc, -- PC for instruction fetch
|
fetch_pc_o => fetch_pc, -- PC for instruction fetch
|
curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
|
curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
|
csr_rdata_o => csr_rdata, -- CSR read data
|
csr_rdata_o => csr_rdata, -- CSR read data
|
|
-- FPU interface --
|
|
fpu_rm_o => fpu_rm, -- rounding mode
|
|
fpu_flags_i => fpu_flags, -- exception flags
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
mext_irq_i => mext_irq_i, -- machine external interrupt
|
mext_irq_i => mext_irq_i, -- machine external interrupt
|
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
| Line 269... |
Line 283... |
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
-- data input --
|
-- data input --
|
mem_i => rdata, -- memory read data
|
mem_i => mem_rdata, -- memory read data
|
alu_i => alu_res, -- ALU result
|
alu_i => alu_res, -- ALU result
|
-- data output --
|
-- data output --
|
rs1_o => rs1, -- operand 1
|
rs1_o => rs1, -- operand 1
|
rs2_o => rs2, -- operand 2
|
rs2_o => rs2, -- operand 2
|
cmp_o => comparator -- comparator status
|
cmp_o => comparator -- comparator status
|
| Line 394... |
Line 408... |
-- required to get the CSR read data into the data path
|
-- required to get the CSR read data into the data path
|
cp_result(3) <= csr_rdata when (CPU_EXTENSION_RISCV_Zicsr = true) else (others => '0');
|
cp_result(3) <= csr_rdata when (CPU_EXTENSION_RISCV_Zicsr = true) else (others => '0');
|
cp_valid(3) <= cp_start(3); -- always assigned even if Zicsr extension is disabled to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(3) <= cp_start(3); -- always assigned even if Zicsr extension is disabled to make sure CPU does not get stalled if there is an accidental access
|
|
|
|
|
-- Co-Processor 4..7: Not Implemented Yet -------------------------------------------------
|
-- Co-Processor 4: Single-Precision Floating-Point Unit ('F' Extension) -------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_cp_fpu_inst_true:
|
|
if (CPU_EXTENSION_RISCV_F = true) generate
|
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock, rising edge
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
|
ctrl_i => ctrl, -- main control bus
|
|
start_i => cp_start(4), -- trigger operation
|
|
-- data input --
|
|
frm_i => fpu_rm, -- rounding mode
|
|
reg_i => rs1, -- rf source
|
|
mem_i => mem_rdata, -- memory read-data
|
|
-- result and status --
|
|
fflags_o => fpu_flags, -- exception flags
|
|
mem_o => fpu_mem_wdata, -- memory write-data
|
|
res_o => cp_result(4), -- operation result
|
|
valid_o => cp_valid(4) -- data output valid
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_cp_fpu_inst_false:
|
|
if (CPU_EXTENSION_RISCV_F = false) generate
|
|
fpu_flags <= (others => '0');
|
|
fpu_mem_wdata <= (others => '0');
|
cp_result(4) <= (others => '0');
|
cp_result(4) <= (others => '0');
|
cp_valid(4) <= '0';
|
cp_valid(4) <= cp_start(4); -- to make sure CPU does not get stalled if there is an accidental access
|
--
|
end generate;
|
|
|
|
|
|
-- Co-Processor 5..7: Not Implemented Yet -------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
cp_result(5) <= (others => '0');
|
cp_result(5) <= (others => '0');
|
cp_valid(5) <= '0';
|
cp_valid(5) <= '0';
|
--
|
--
|
cp_result(6) <= (others => '0');
|
cp_result(6) <= (others => '0');
|
cp_valid(6) <= '0';
|
cp_valid(6) <= '0';
|
| Line 434... |
Line 477... |
--
|
--
|
ma_instr_o => ma_instr, -- misaligned instruction address
|
ma_instr_o => ma_instr, -- misaligned instruction address
|
be_instr_o => be_instr, -- bus error on instruction access
|
be_instr_o => be_instr, -- bus error on instruction access
|
-- cpu data access interface --
|
-- cpu data access interface --
|
addr_i => alu_add, -- ALU.add result -> access address
|
addr_i => alu_add, -- ALU.add result -> access address
|
wdata_i => rs2, -- write data
|
wdata_i => mem_wdata, -- write data
|
rdata_o => rdata, -- read data
|
rdata_o => mem_rdata, -- read data
|
mar_o => mar, -- current memory address register
|
mar_o => mar, -- current memory address register
|
d_wait_o => bus_d_wait, -- wait for access to complete
|
d_wait_o => bus_d_wait, -- wait for access to complete
|
--
|
--
|
ma_load_o => ma_load, -- misaligned load data address
|
ma_load_o => ma_load, -- misaligned load data address
|
ma_store_o => ma_store, -- misaligned store data address
|
ma_store_o => ma_store, -- misaligned store data address
|
| Line 472... |
Line 515... |
d_bus_err_i => d_bus_err_i, -- bus transfer error
|
d_bus_err_i => d_bus_err_i, -- bus transfer error
|
d_bus_fence_o => d_bus_fence_o, -- fence operation
|
d_bus_fence_o => d_bus_fence_o, -- fence operation
|
d_bus_lock_o => d_bus_lock_o -- locked/exclusive access
|
d_bus_lock_o => d_bus_lock_o -- locked/exclusive access
|
);
|
);
|
|
|
|
-- memory write data --
|
|
mem_wdata <= fpu_mem_wdata when ((CPU_EXTENSION_RISCV_F = true) and (ctrl(ctrl_bus_wd_sel_c) = '1')) else rs2;
|
|
|
-- current privilege level --
|
-- current privilege level --
|
i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
|
|
|
|
