| Line 66... |
Line 66... |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
|
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
TINY_SHIFT_EN : boolean := false; -- use tiny (single-bit) shifter for shift operations
|
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
| Line 118... |
Line 118... |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i : in std_ulogic_vector(15 downto 0) := (others => '0');
|
firq_i : in std_ulogic_vector(15 downto 0) := (others => '0');
|
firq_ack_o : out std_ulogic_vector(15 downto 0);
|
|
-- debug mode (halt) request --
|
-- debug mode (halt) request --
|
db_halt_req_i : in std_ulogic := '0'
|
db_halt_req_i : in std_ulogic := '0'
|
);
|
);
|
end neorv32_cpu;
|
end neorv32_cpu;
|
|
|
| Line 135... |
Line 134... |
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
|
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
|
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
|
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
|
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
|
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
|
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
|
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
|
signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
|
signal alu_idone : std_ulogic; -- iterative alu operation done
|
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
|
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
|
signal bus_d_wait : std_ulogic; -- wait for current bus data access
|
signal bus_d_wait : std_ulogic; -- wait for current bus data access
|
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
signal ma_instr : std_ulogic; -- misaligned instruction address
|
signal ma_instr : std_ulogic; -- misaligned instruction address
|
| Line 149... |
Line 148... |
signal be_instr : std_ulogic; -- bus error on instruction access
|
signal be_instr : std_ulogic; -- bus error on instruction access
|
signal be_load : std_ulogic; -- bus error on load data access
|
signal be_load : std_ulogic; -- bus error on load data access
|
signal be_store : std_ulogic; -- bus error on store data access
|
signal be_store : std_ulogic; -- bus error on store data access
|
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
signal fpu_rm : std_ulogic_vector(2 downto 0); -- FPU rounding mode
|
|
signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
|
signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
|
|
|
-- co-processor interface --
|
|
signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
|
|
signal cp_valid : std_ulogic_vector(7 downto 0); -- co-processor i done
|
|
signal cp_result : cp_data_if_t; -- co-processor result
|
|
|
|
-- pmp interface --
|
-- pmp interface --
|
signal pmp_addr : pmp_addr_if_t;
|
signal pmp_addr : pmp_addr_if_t;
|
signal pmp_ctrl : pmp_ctrl_if_t;
|
signal pmp_ctrl : pmp_ctrl_if_t;
|
|
|
begin
|
begin
|
|
|
|
-- CPU ISA Configuration ---------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
assert false report
|
|
"NEORV32 CPU ISA Configuration (MARCH): " &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_E, "RV32E", "RV32I") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_A, "A", "") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_Zicsr, "_Zicsr", "") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
|
|
cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_Debug", "") &
|
|
""
|
|
severity note;
|
|
|
|
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- hardware reset notifier --
|
-- hardware reset notifier --
|
assert not ((dedicated_reset_c = false) and (def_rst_val_c = '-')) report "NEORV32 CPU CONFIG NOTE: Using NO dedicated hardware reset for uncritical registers (default, might reduce area footprint). Set the package constant <dedicated_reset_c> to TRUE if you need a defined reset value." severity note;
|
assert not (dedicated_reset_c = false) report "NEORV32 CPU CONFIG NOTE: Implementing NO dedicated hardware reset for uncritical registers (default, might reduce area). Set package constant <dedicated_reset_c> = TRUE to configure a DEFINED reset value for all CPU registers." severity note;
|
assert not ((dedicated_reset_c = true) and (def_rst_val_c = '0')) report "NEORV32 CPU CONFIG NOTE: Using defined hardware reset for uncritical registers (non-default, reset-to-zero, might increase area footprint)." severity note;
|
assert not (dedicated_reset_c = true) report "NEORV32 CPU CONFIG NOTE: Implementing defined hardware reset for uncritical registers (non-default, reset-to-zero, might increase area)." severity note;
|
assert not ((def_rst_val_c /= '-') and (def_rst_val_c /= '0')) report "NEORV32 CPU CONFIG ERROR! Invalid configuration of package <def_rst_val_c> constant (has to be '-' or '0')." severity error;
|
assert not ((def_rst_val_c /= '-') and (def_rst_val_c /= '0')) report "NEORV32 CPU CONFIG ERROR! Invalid configuration of package <def_rst_val_c> constant (has to be '-' or '0')." severity error;
|
|
|
-- CSR system --
|
-- CSR system --
|
assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/privileged features available when <CPU_EXTENSION_RISCV_Zicsr> = false." severity warning;
|
assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/privileged features available when <CPU_EXTENSION_RISCV_Zicsr> = false." severity warning;
|
|
|
| Line 191... |
Line 202... |
-- PMP regions check --
|
-- PMP regions check --
|
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out xf valid range (0..64)." severity error;
|
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out xf valid range (0..64)." severity error;
|
-- PMP granularity --
|
-- PMP granularity --
|
assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be a power of two." severity error;
|
assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be a power of two." severity error;
|
assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be >= 8 bytes." severity error;
|
assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be >= 8 bytes." severity error;
|
-- PMP notifier --
|
|
assert not (PMP_NUM_REGIONS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing physical memory protection (PMP) with " & integer'image(PMP_NUM_REGIONS) & " regions and a minimal granularity of " & integer'image(PMP_MIN_GRANULARITY) & " bytes." severity note;
|
|
-- PMP requires Zicsr extension --
|
-- PMP requires Zicsr extension --
|
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
|
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
|
|
|
-- HPM counters check --
|
-- HPM counters check --
|
assert not (HPM_NUM_CNTS > 29) report "NEORV32 CPU CONFIG ERROR! Number of HPM counters <HPM_NUM_CNTS> out of valid range (0..29)." severity error;
|
assert not (HPM_NUM_CNTS > 29) report "NEORV32 CPU CONFIG ERROR! Number of HPM counters <HPM_NUM_CNTS> out of valid range (0..29)." severity error;
|
assert not ((HPM_CNT_WIDTH < 0) or (HPM_CNT_WIDTH > 64)) report "NEORV32 CPU CONFIG ERROR! HPM counter width <HPM_CNT_WIDTH> has to be 0..64 bit." severity error;
|
assert not ((HPM_CNT_WIDTH < 0) or (HPM_CNT_WIDTH > 64)) report "NEORV32 CPU CONFIG ERROR! HPM counter width <HPM_CNT_WIDTH> has to be 0..64 bit." severity error;
|
-- HPM counters notifier --
|
|
assert not (HPM_NUM_CNTS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing " & integer'image(HPM_NUM_CNTS) & " HPM counters (each " & integer'image(HPM_CNT_WIDTH) & "-bit wide)." severity note;
|
|
-- HPM CNT requires Zicsr extension --
|
-- HPM CNT requires Zicsr extension --
|
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors (HPM) require <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
|
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors (HPM) require <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
|
|
|
|
-- Mul-extension --
|
|
assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <ZMMUL> extensions cannot co-exist!" severity error;
|
|
|
-- Debug mode --
|
-- Debug mode --
|
assert not (CPU_EXTENSION_RISCV_DEBUG = true) report "NEORV32 CPU CONFIG NOTE: Implementing RISC-V DEBUG MODE extension." severity note;
|
|
assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
|
assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
|
|
|
|
|
-- Control Unit ---------------------------------------------------------------------------
|
-- Control Unit ---------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 225... |
Line 234... |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
|
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
|
CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
|
CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
|
-- Extension Options --
|
-- Extension Options --
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
| Line 241... |
Line 251... |
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_o => ctrl, -- main control bus
|
ctrl_o => ctrl, -- main control bus
|
-- status input --
|
-- status input --
|
alu_wait_i => alu_wait, -- wait for ALU
|
alu_idone_i => alu_idone, -- ALU iterative operation done
|
bus_i_wait_i => bus_i_wait, -- wait for bus
|
bus_i_wait_i => bus_i_wait, -- wait for bus
|
bus_d_wait_i => bus_d_wait, -- wait for bus
|
bus_d_wait_i => bus_d_wait, -- wait for bus
|
excl_state_i => excl_state, -- atomic/exclusive access lock status
|
excl_state_i => excl_state, -- atomic/exclusive access lock status
|
-- data input --
|
-- data input --
|
instr_i => instr, -- instruction
|
instr_i => instr, -- instruction
|
| Line 256... |
Line 266... |
imm_o => imm, -- immediate
|
imm_o => imm, -- immediate
|
fetch_pc_o => fetch_pc, -- PC for instruction fetch
|
fetch_pc_o => fetch_pc, -- PC for instruction fetch
|
curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
|
curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
|
csr_rdata_o => csr_rdata, -- CSR read data
|
csr_rdata_o => csr_rdata, -- CSR read data
|
-- FPU interface --
|
-- FPU interface --
|
fpu_rm_o => fpu_rm, -- rounding mode
|
|
fpu_flags_i => fpu_flags, -- exception flags
|
fpu_flags_i => fpu_flags, -- exception flags
|
-- debug mode (halt) request --
|
-- debug mode (halt) request --
|
db_halt_req_i => db_halt_req_i,
|
db_halt_req_i => db_halt_req_i,
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
| Line 268... |
Line 277... |
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
mtime_irq_i => mtime_irq_i, -- machine timer interrupt
|
-- non-maskable interrupt --
|
-- non-maskable interrupt --
|
nm_irq_i => nm_irq_i, -- nmi
|
nm_irq_i => nm_irq_i, -- nmi
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i => firq_i, -- fast interrupt trigger
|
firq_i => firq_i, -- fast interrupt trigger
|
firq_ack_o => firq_ack_o, -- fast interrupt acknowledge mask
|
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i => time_i, -- current system time
|
time_i => time_i, -- current system time
|
-- physical memory protection --
|
-- physical memory protection --
|
pmp_addr_o => pmp_addr, -- addresses
|
pmp_addr_o => pmp_addr, -- addresses
|
pmp_ctrl_o => pmp_ctrl, -- configs
|
pmp_ctrl_o => pmp_ctrl, -- configs
|
| Line 312... |
Line 320... |
|
|
-- ALU ------------------------------------------------------------------------------------
|
-- ALU ------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_alu_inst: neorv32_cpu_alu
|
neorv32_cpu_alu_inst: neorv32_cpu_alu
|
generic map (
|
generic map (
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
-- RISC-V CPU Extensions --
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
|
TINY_SHIFT_EN => TINY_SHIFT_EN -- use tiny (single-bit) shifter for shift operations
|
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
|
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
|
-- Extension Options --
|
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
|
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
| Line 326... |
Line 338... |
-- data input --
|
-- data input --
|
rs1_i => rs1, -- rf source 1
|
rs1_i => rs1, -- rf source 1
|
rs2_i => rs2, -- rf source 2
|
rs2_i => rs2, -- rf source 2
|
pc2_i => curr_pc, -- delayed PC
|
pc2_i => curr_pc, -- delayed PC
|
imm_i => imm, -- immediate
|
imm_i => imm, -- immediate
|
|
csr_i => csr_rdata, -- CSR read data
|
|
cmp_i => comparator, -- comparator status
|
-- data output --
|
-- data output --
|
res_o => alu_res, -- ALU result
|
res_o => alu_res, -- ALU result
|
add_o => alu_add, -- address computation result
|
add_o => alu_add, -- address computation result
|
-- co-processor interface --
|
fpu_flags_o => fpu_flags, -- FPU exception flags
|
cp_start_o => cp_start, -- trigger co-processor i
|
|
cp_valid_i => cp_valid, -- co-processor i done
|
|
cp_result_i => cp_result, -- co-processor result
|
|
-- status --
|
-- status --
|
wait_o => alu_wait -- busy due to iterative processing units
|
idone_o => alu_idone -- iterative processing units done?
|
);
|
);
|
|
|
|
|
-- Co-Processor 0: CSR (Read) Access ('Zicsr' Extension) ----------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
-- "pseudo" co-processor for CSR *read* access operations
|
|
-- required to get CSR read data into the data path
|
|
cp_result(0) <= csr_rdata when (CPU_EXTENSION_RISCV_Zicsr = true) else (others => '0');
|
|
cp_valid(0) <= cp_start(0); -- always assigned even if Zicsr extension is disabled to make sure CPU does not get stalled if there is an accidental access
|
|
|
|
|
|
-- Co-Processor 1: Integer Multiplication/Division ('M' Extension) ------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_cp_muldiv_inst_true:
|
|
if (CPU_EXTENSION_RISCV_M = true) generate
|
|
neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
|
|
generic map (
|
|
FAST_MUL_EN => FAST_MUL_EN -- use DSPs for faster multiplication
|
|
)
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock, rising edge
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
|
ctrl_i => ctrl, -- main control bus
|
|
start_i => cp_start(1), -- trigger operation
|
|
-- data input --
|
|
rs1_i => rs1, -- rf source 1
|
|
rs2_i => rs2, -- rf source 2
|
|
-- result and status --
|
|
res_o => cp_result(1), -- operation result
|
|
valid_o => cp_valid(1) -- data output valid
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_cp_muldiv_inst_false:
|
|
if (CPU_EXTENSION_RISCV_M = false) generate
|
|
cp_result(1) <= (others => '0');
|
|
cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
|
|
end generate;
|
|
|
|
|
|
-- Co-Processor 2: reseverd ---------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
cp_result(2) <= (others => '0');
|
|
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
|
|
|
|
|
|
-- Co-Processor 3: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_cp_fpu_inst_true:
|
|
if (CPU_EXTENSION_RISCV_Zfinx = true) generate
|
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock, rising edge
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
|
ctrl_i => ctrl, -- main control bus
|
|
start_i => cp_start(3), -- trigger operation
|
|
-- data input --
|
|
frm_i => fpu_rm, -- rounding mode
|
|
cmp_i => comparator, -- comparator status
|
|
rs1_i => rs1, -- rf source 1
|
|
rs2_i => rs2, -- rf source 2
|
|
-- result and status --
|
|
res_o => cp_result(3), -- operation result
|
|
fflags_o => fpu_flags, -- exception flags
|
|
valid_o => cp_valid(3) -- data output valid
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_cp_fpu_inst_false:
|
|
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
|
|
cp_result(3) <= (others => '0');
|
|
fpu_flags <= (others => '0');
|
|
cp_valid(3) <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access
|
|
end generate;
|
|
|
|
|
|
-- Co-Processor 4,5,6,7: Not Implemented --------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
cp_result(4) <= (others => '0');
|
|
cp_valid(4) <= '0';
|
|
--
|
|
cp_result(5) <= (others => '0');
|
|
cp_valid(5) <= '0';
|
|
--
|
|
cp_result(6) <= (others => '0');
|
|
cp_valid(6) <= '0';
|
|
--
|
|
cp_result(7) <= (others => '0');
|
|
cp_valid(7) <= '0';
|
|
|
|
|
|
-- Bus Interface Unit ---------------------------------------------------------------------
|
-- Bus Interface Unit ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
generic map (
|
generic map (
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
| Line 464... |
Line 385... |
ma_store_o => ma_store, -- misaligned store data address
|
ma_store_o => ma_store, -- misaligned store data address
|
be_load_o => be_load, -- bus error on load data access
|
be_load_o => be_load, -- bus error on load data access
|
be_store_o => be_store, -- bus error on store data access
|
be_store_o => be_store, -- bus error on store data access
|
-- physical memory protection --
|
-- physical memory protection --
|
pmp_addr_i => pmp_addr, -- addresses
|
pmp_addr_i => pmp_addr, -- addresses
|
pmp_ctrl_i => pmp_ctrl, -- configs
|
pmp_ctrl_i => pmp_ctrl, -- configurations
|
-- instruction bus --
|
-- instruction bus --
|
i_bus_addr_o => i_bus_addr_o, -- bus access address
|
i_bus_addr_o => i_bus_addr_o, -- bus access address
|
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
|
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
|
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
|
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
