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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu is
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entity neorv32_cpu is
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generic (
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generic (
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-- General --
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-- General --
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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HW_THREAD_ID : natural; -- hardware thread id (32-bit)
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
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CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
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CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
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CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
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CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_NUM_REGIONS : natural; -- number of regions (0..64)
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (0..64)
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HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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sleep_o : out std_ulogic; -- cpu is in sleep mode when set
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sleep_o : out std_ulogic; -- cpu is in sleep mode when set
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-- instruction bus interface --
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-- instruction bus interface --
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_lock_o : out std_ulogic; -- exclusive access request
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i_bus_lock_o : out std_ulogic; -- exclusive access request
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i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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-- data bus interface --
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-- data bus interface --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_lock_o : out std_ulogic; -- exclusive access request
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d_bus_lock_o : out std_ulogic; -- exclusive access request
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d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- non-maskable interrupt --
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-- non-maskable interrupt --
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nm_irq_i : in std_ulogic := '0'; -- NMI
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nm_irq_i : in std_ulogic; -- NMI
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic;-- machine software interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mext_irq_i : in std_ulogic;-- machine external interrupt
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
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mtime_irq_i : in std_ulogic;-- machine timer interrupt
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(15 downto 0) := (others => '0');
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firq_i : in std_ulogic_vector(15 downto 0);
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-- debug mode (halt) request --
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-- debug mode (halt) request --
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db_halt_req_i : in std_ulogic := '0'
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db_halt_req_i : in std_ulogic
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);
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);
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end neorv32_cpu;
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end neorv32_cpu;
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architecture neorv32_cpu_rtl of neorv32_cpu is
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architecture neorv32_cpu_rtl of neorv32_cpu is
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-- U-extension requires Zicsr extension --
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-- U-extension requires Zicsr extension --
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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-- Instruction prefetch buffer size --
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-- Instruction prefetch buffer size --
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assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
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assert not (is_power_of_two_f(CPU_IPB_ENTRIES) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <CPU_IPB_ENTRIES> has to be a power of two." severity error;
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-- Co-processor timeout counter (for debugging only) --
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-- Co-processor timeout counter (for debugging only) --
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assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
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assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
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-- PMP regions check --
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-- PMP regions check --
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CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
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CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
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CPU_DEBUG_ADDR => CPU_DEBUG_ADDR, -- cpu debug mode start address
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CPU_DEBUG_ADDR => CPU_DEBUG_ADDR, -- cpu debug mode start address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
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CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
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CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
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-- Extension Options --
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-- Extension Options --
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CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
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CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29)
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HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29)
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