| Line 154... |
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next executed instruction)
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signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
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signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
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-- pmp interface --
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-- pmp interface --
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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-- data output --
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-- data output --
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imm_o => imm, -- immediate
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imm_o => imm, -- immediate
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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next_pc_o => next_pc, -- next PC (corresponding to next instruction)
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csr_rdata_o => csr_rdata, -- CSR read data
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csr_rdata_o => csr_rdata, -- CSR read data
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-- FPU interface --
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-- FPU interface --
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fpu_flags_i => fpu_flags, -- exception flags
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fpu_flags_i => fpu_flags, -- exception flags
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-- debug mode (halt) request --
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-- debug mode (halt) request --
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db_halt_req_i => db_halt_req_i,
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db_halt_req_i => db_halt_req_i,
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- data input --
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-- data input --
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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pc2_i => curr_pc, -- delayed PC
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pc_i => curr_pc, -- current PC
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pc2_i => next_pc, -- next PC
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imm_i => imm, -- immediate
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imm_i => imm, -- immediate
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csr_i => csr_rdata, -- CSR read data
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csr_i => csr_rdata, -- CSR read data
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-- data output --
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-- data output --
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cmp_o => comparator, -- comparator status
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cmp_o => comparator, -- comparator status
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res_o => alu_res, -- ALU result
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res_o => alu_res, -- ALU result
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