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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # NEORV32 CPU: #
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-- # NEORV32 CPU: #
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-- # * neorv32_cpu.vhd - CPU top entity #
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-- # * neorv32_cpu.vhd - CPU top entity #
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-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
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-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
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-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor #
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-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor #
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-- # * neorv32_cpu_cp_cfu.vhd - Custom instructions co-processor #
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-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor #
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-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor #
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-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor #
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-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor #
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-- # * neorv32_cpu_cp_shifter.vhd - Base ISA shifter unit #
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-- # * neorv32_cpu_cp_shifter.vhd - Base ISA shifter unit #
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-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
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-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
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-- # * neorv32_cpu_control.vhd - CPU control and CSR system #
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-- # * neorv32_cpu_control.vhd - CPU control and CSR system #
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CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
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CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
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CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
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CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
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CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
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CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr, "_Zicntr", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm, "_Zihpm", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu, "_Zxcfu", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_DEBUG", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_DEBUG", "") &
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""
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""
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severity note;
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severity note;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_Zihpm = true)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors extension <CPU_EXTENSION_RISCV_Zihpm> requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_Zihpm = true)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors extension <CPU_EXTENSION_RISCV_Zihpm> requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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-- Mul-extension --
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-- Mul-extension --
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assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error;
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assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error;
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-- Custom Functions Unit --
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assert not (CPU_EXTENSION_RISCV_Zxcfu = true) report "NEORV32 CPU CONFIG NOTE: Implementing Custom Functions Unit (CFU) as <Zxcfu> ISA extension." severity note;
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-- Debug mode --
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-- Debug mode --
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zifencei> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zifencei> extension to be enabled." severity error;
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-- fast multiplication option --
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-- fast multiplication option --
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
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CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters?
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CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
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CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
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CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
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-- Extension Options --
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-- Tuning Options --
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FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
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CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH => CPU_CNT_WIDTH, -- total width of CPU cycle and instret counters (0..64)
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CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2
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CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 2
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension?
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CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
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FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
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FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
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)
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)
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port map (
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port map (
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