URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_alu.vhd] - Diff between revs 9 and 11

Rev 9	Rev 11
Line 40...	Line 40...

`library neorv32;`	`library neorv32;`
`use neorv32.neorv32_package.all;`	`use neorv32.neorv32_package.all;`

`entity neorv32_cpu_alu is`	`entity neorv32_cpu_alu is`
	`generic (`
	`CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?`
	`);`
`port (`	`port (`
`-- global control --`	`-- global control --`
`clk_i : in std_ulogic; -- global clock, rising edge`	`clk_i : in std_ulogic; -- global clock, rising edge`
`rstn_i : in std_ulogic; -- global reset, low-active, async`	`rstn_i : in std_ulogic; -- global reset, low-active, async`
`ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus`	`ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus`
Line 198...	Line 201...
`cp_cmd_ff <= '0';`	`cp_cmd_ff <= '0';`
`cp_busy <= '0';`	`cp_busy <= '0';`
`cp_rb_ff0 <= '0';`	`cp_rb_ff0 <= '0';`
`cp_rb_ff1 <= '0';`	`cp_rb_ff1 <= '0';`
`elsif rising_edge(clk_i) then`	`elsif rising_edge(clk_i) then`
`if (ctrl_i(ctrl_sys_m_ext_en_c) = '1') then -- FIXME add second cp (floating point stuff?)`	`if (CPU_EXTENSION_RISCV_M = true) then -- FIXME add second cp (floating point stuff?)`
`cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);`	`cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);`
`cp_rb_ff0 <= '0';`	`cp_rb_ff0 <= '0';`
`cp_rb_ff1 <= cp_rb_ff0;`	`cp_rb_ff1 <= cp_rb_ff0;`
`if (cp_start = '1') then`	`if (cp_start = '1') then`
`cp_busy <= '1';`	`cp_busy <= '1';`