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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_alu.vhd] - Diff between revs 25 and 26

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Rev 25 Rev 26
Line 118... Line 118...
 
 
  -- Operand Mux ----------------------------------------------------------------------------
  -- Operand Mux ----------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
  input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
  begin
  begin
    -- opa (first ALU input operand) --
    -- operand a (first ALU input operand) --
    case ctrl_i(ctrl_alu_opa_mux_msb_c downto ctrl_alu_opa_mux_lsb_c) is
    case ctrl_i(ctrl_alu_opa_mux_msb_c downto ctrl_alu_opa_mux_lsb_c) is
      when "00"   => opa <= rs1_i;
      when "00"   => opa <= rs1_i;
      when "01"   => opa <= pc2_i;
      when "01"   => opa <= pc2_i;
      when others => opa <= csr_i;
      when others => opa <= csr_i;
    end case;
    end case;
    -- opb (second ALU input operand) --
    -- operand b (second ALU input operand) --
    if (ctrl_i(ctrl_alu_opb_mux_c) = '0') then
    if (ctrl_i(ctrl_alu_opb_mux_c) = '0') then
      opb <= rs2_i;
      opb <= rs2_i;
    else
    else
      opb <= imm_i;
      opb <= imm_i;
    end if;
    end if;
    -- opc (second operand for comparison and SUB) --
    -- operand c (third ALU input operand for comparison and SUB) --
    if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
    if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
      opc <= imm_i;
 
    else
 
      opc <= rs2_i;
      opc <= rs2_i;
 
    else
 
      opc <= imm_i;
    end if;
    end if;
  end process input_op_mux;
  end process input_op_mux;
 
 
 
 
  -- Comparator Unit ------------------------------------------------------------------------
  -- Comparator Unit ------------------------------------------------------------------------
Line 148... Line 148...
  cmp_opy  <= (opc(opc'left)     and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
  cmp_opy  <= (opc(opc'left)     and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
  cmp_sub  <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
  cmp_sub  <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
  cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a "less"
  cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a "less"
  sub_res  <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
  sub_res  <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
 
 
  -- equal (x = y) --
  -- equal (for branch check only) --
  cmp_equal <= '1' when (rs1_i = opc) else '0';
  cmp_equal <= '1' when (rs1_i = rs2_i) else '0';
 
 
  -- output for branch condition evaluation -
  -- output for branch condition evaluation --
  cmp_o(alu_cmp_equal_c) <= cmp_equal;
  cmp_o(alu_cmp_equal_c) <= cmp_equal;
  cmp_o(alu_cmp_less_c)  <= cmp_less;
  cmp_o(alu_cmp_less_c)  <= cmp_less;
 
 
 
 
  -- Binary Adder ---------------------------------------------------------------------------
  -- Binary Adder ---------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  add_res <= std_ulogic_vector(unsigned(opa) + unsigned(opb));
  add_res <= std_ulogic_vector(unsigned(opa) + unsigned(opb));
  add_o   <= add_res; -- direct output
  add_o   <= add_res; -- direct output (for PC modification)
 
 
 
 
  -- Iterative Shifter Unit -----------------------------------------------------------------
  -- Iterative Shifter Unit -----------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  shifter_unit: process(rstn_i, clk_i)
  shifter_unit: process(rstn_i, clk_i)

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