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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter. #
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-- # Main data and address ALU and co-processor interface/arbiter. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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-- co-processor interface --
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-- co-processor interface --
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cp0_start_o : out std_ulogic; -- trigger co-processor 0
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cp0_start_o : out std_ulogic; -- trigger co-processor 0
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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--
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--
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal arith_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal arith_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal logic_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal logic_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
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-- shifter --
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-- shifter --
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type shifter_t is record
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type shifter_t is record
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cmd : std_ulogic;
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cmd : std_ulogic;
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cmd_ff : std_ulogic;
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cmd_ff : std_ulogic;
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start : std_ulogic;
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start : std_ulogic;
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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-- Comparator Unit ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opy <= (rs2_i(rs2_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2_i;
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cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy)); -- less than (x < y)
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cmp_o(alu_cmp_equal_c) <= '1' when (rs1_i = rs2_i) else '0';
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cmp_o(alu_cmp_less_c) <= cmp_sub(cmp_sub'left); -- less = carry (borrow)
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-- Binary Adder/Subtractor ----------------------------------------------------------------
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-- Binary Adder/Subtractor ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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binary_arithmetic_core: process(ctrl_i, opa, opb)
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binary_arithmetic_core: process(ctrl_i, opa, opb)
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variable cin_v : std_ulogic_vector(0 downto 0);
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variable cin_v : std_ulogic_vector(0 downto 0);
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variable op_a_v : std_ulogic_vector(data_width_c downto 0);
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variable op_a_v : std_ulogic_vector(data_width_c downto 0);
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variable res_v : std_ulogic_vector(data_width_c downto 0);
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variable res_v : std_ulogic_vector(data_width_c downto 0);
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begin
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begin
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-- operand sign-extension --
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-- operand sign-extension --
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op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa;
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op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa;
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op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb;
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op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb;
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-- add/sub(slt) select --
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-- add/sub(slt) select --
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if (ctrl_i(ctrl_alu_addsub_c) = '1') then -- subtraction
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if (ctrl_i(ctrl_alu_addsub_c) = '1') then -- subtraction
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op_y_v := not op_b_v;
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op_y_v := not op_b_v;
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cin_v(0) := '1';
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cin_v(0) := '1';
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else -- addition
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else -- addition
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op_y_v := op_b_v;
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op_y_v := op_b_v;
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cin_v(0) := '0';
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cin_v(0) := '0';
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end if;
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end if;
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-- adder core (result + carry/borrow) --
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-- adder core (result + carry/borrow) --
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addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
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addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
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end process binary_arithmetic_core;
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end process binary_arithmetic_core;
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-- direct output of address result --
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-- direct output of address result --
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-- --------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------
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-- Barrel shifter (huge but fast)
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-- Barrel shifter (huge but fast)
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-- --------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------
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else
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else
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-- operands and cycle control --
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-- operands and cycle control --
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if (shifter.start = '1') then -- trigger new shift
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if (shifter.start = '1') then -- trigger new shift
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shifter.bs_d_in <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
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shifter.bs_d_in <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
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shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.cnt <= (others => '0');
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shifter.cnt <= (others => '0');
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-- shift operation running? --
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-- shift operation running? --
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shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
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shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
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shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
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shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
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-- Coprocessor Arbiter --------------------------------------------------------------------
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-- Co-Processor Arbiter -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Interface:
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-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
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-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
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cp_arbiter: process(rstn_i, clk_i)
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cp_arbiter: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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-- co-processor operation (still) running? --
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-- co-processor operation (still) running? --
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cp_ctrl.halt <= (cp_ctrl.busy and (not (cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i))) or cp_ctrl.start;
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cp_ctrl.halt <= (cp_ctrl.busy and (not (cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i))) or cp_ctrl.start;
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-- co-processor result --
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-- co-processor result --
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cp_read_back: process(clk_i)
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begin
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if rising_edge(clk_i) then
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cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0
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cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0
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end if;
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end process cp_read_back;
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-- ALU Logic Core -------------------------------------------------------------------------
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-- ALU Logic Core -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_logic_core: process(ctrl_i, rs1_i, opb)
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alu_logic_core: process(ctrl_i, rs1_i, opb)
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