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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_alu is
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entity neorv32_cpu_alu is
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generic (
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_M : boolean := false -- implement mul/div extension?
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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end neorv32_cpu_alu;
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end neorv32_cpu_alu;
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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-- operands --
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-- operands --
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signal opa, opb, opc, pc_inc : std_ulogic_vector(data_width_c-1 downto 0);
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signal opa, opb, opc : std_ulogic_vector(data_width_c-1 downto 0);
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-- results --
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-- results --
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signal add_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal add_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
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begin
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begin
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-- Operand Mux ----------------------------------------------------------------------------
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-- Operand Mux ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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input_op_mux: process(ctrl_i, csr_i, pc2_i, pc_i, rs1_i, rs2_i, imm_i, pc_inc)
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input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
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begin
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begin
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-- opa (first ALU input operand) --
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-- opa (first ALU input operand) --
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case ctrl_i(ctrl_alu_opa_mux_msb_c downto ctrl_alu_opa_mux_lsb_c) is
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if (ctrl_i(ctrl_alu_opa_mux_msb_c) = '0') then
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when "00" => opa <= rs1_i;
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if (ctrl_i(ctrl_alu_opa_mux_lsb_c) = '0') then
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when "01" => opa <= pc2_i;
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opa <= rs1_i;
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when "10" => opa <= csr_i;
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else
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when others => opa <= pc_i;
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opa <= pc2_i;
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end case;
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end if;
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else
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opa <= csr_i;
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end if;
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-- opb (second ALU input operand) --
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-- opb (second ALU input operand) --
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case ctrl_i(ctrl_alu_opb_mux_msb_c downto ctrl_alu_opb_mux_lsb_c) is
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if (ctrl_i(ctrl_alu_opb_mux_msb_c) = '0') then
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when "00" => opb <= rs2_i;
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if (ctrl_i(ctrl_alu_opb_mux_lsb_c) = '0') then
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when "01" => opb <= imm_i;
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opb <= rs2_i;
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when "10" => opb <= rs1_i;
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else
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when others => opb <= pc_inc;
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opb <= imm_i;
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end case;
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end if;
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else
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opb <= rs1_i;
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end if;
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-- opc (second operand for comparison (and SUB)) --
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-- opc (second operand for comparison (and SUB)) --
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if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
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if (ctrl_i(ctrl_alu_opc_mux_c) = '0') then
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opc <= imm_i;
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opc <= imm_i;
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else
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else
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opc <= rs2_i;
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opc <= rs2_i;
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end if;
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end if;
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end process input_op_mux;
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end process input_op_mux;
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-- PC increment --
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pc_inc <= x"00000002" when (CPU_EXTENSION_RISCV_C = true) else x"00000004";
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-- Comparator Unit ------------------------------------------------------------------------
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-- Comparator Unit ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- less than (x < y) --
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-- less than (x < y) --
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cp_cmd_ff <= '0';
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cp_cmd_ff <= '0';
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cp_busy <= '0';
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cp_busy <= '0';
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cp_rb_ff0 <= '0';
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cp_rb_ff0 <= '0';
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cp_rb_ff1 <= '0';
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cp_rb_ff1 <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (CPU_EXTENSION_RISCV_M = true) then
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if (ctrl_i(ctrl_sys_m_ext_en_c) = '1') then
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cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);
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cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);
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cp_rb_ff0 <= '0';
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cp_rb_ff0 <= '0';
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cp_rb_ff1 <= cp_rb_ff0;
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cp_rb_ff1 <= cp_rb_ff0;
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if (cp_start = '1') then
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if (cp_start = '1') then
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cp_busy <= '1';
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cp_busy <= '1';
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