| Line 61... |
Line 61... |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
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fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
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-- status --
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-- status --
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idone_o : out std_ulogic -- iterative processing units done?
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idone_o : out std_ulogic -- iterative processing units done?
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);
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);
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end neorv32_cpu_alu;
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end neorv32_cpu_alu;
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp : std_ulogic_vector(1 downto 0); -- comparator status
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-- operands --
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-- operands --
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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-- results --
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-- results --
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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| Line 100... |
Line 105... |
signal cp_valid : std_ulogic_vector(3 downto 0); -- co-processor i done
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signal cp_valid : std_ulogic_vector(3 downto 0); -- co-processor i done
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signal cp_result : cp_data_if_t; -- co-processor result
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signal cp_result : cp_data_if_t; -- co-processor result
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begin
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begin
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-- Operand Mux ----------------------------------------------------------------------------
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-- Comparator Unit (for conditional branches) ---------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opy <= (rs2_i(rs2_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2_i;
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cmp(cmp_equal_c) <= '1' when (rs1_i = rs2_i) else '0';
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cmp(cmp_less_c) <= '1' when (signed(cmp_opx) < signed(cmp_opy)) else '0';
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cmp_o <= cmp;
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-- ALU Input Operand Mux ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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| Line 277... |
Line 292... |
cp_result(1) <= (others => '0');
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cp_result(1) <= (others => '0');
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cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
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cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
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end generate;
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end generate;
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-- Co-Processor 2: Bit-Manipulation Unit ('Zbb' Extension) --------------------------------
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-- Co-Processor 2: Bit-Manipulation Unit ('B'/'Zbb' Extension) ----------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_cp_bitmanip_inst_true:
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neorv32_cpu_cp_bitmanip_inst_true:
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if (CPU_EXTENSION_RISCV_Zbb = true) generate
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if (CPU_EXTENSION_RISCV_Zbb = true) generate
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neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
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neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
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generic map (
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generic map (
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| Line 292... |
Line 307... |
clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl_i, -- main control bus
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ctrl_i => ctrl_i, -- main control bus
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start_i => cp_start(2), -- trigger operation
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start_i => cp_start(2), -- trigger operation
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-- data input --
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-- data input --
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cmp_i => cmp_i, -- comparator status
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cmp_i => cmp, -- comparator status
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rs1_i => rs1_i, -- rf source 1
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rs1_i => rs1_i, -- rf source 1
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rs2_i => rs2_i, -- rf source 2
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rs2_i => rs2_i, -- rf source 2
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-- result and status --
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-- result and status --
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res_o => cp_result(2), -- operation result
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res_o => cp_result(2), -- operation result
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valid_o => cp_valid(2) -- data output valid
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valid_o => cp_valid(2) -- data output valid
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| Line 320... |
Line 335... |
clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl_i, -- main control bus
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ctrl_i => ctrl_i, -- main control bus
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start_i => cp_start(3), -- trigger operation
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start_i => cp_start(3), -- trigger operation
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-- data input --
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-- data input --
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cmp_i => cmp_i, -- comparator status
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cmp_i => cmp, -- comparator status
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rs1_i => rs1_i, -- rf source 1
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rs1_i => rs1_i, -- rf source 1
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rs2_i => rs2_i, -- rf source 2
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rs2_i => rs2_i, -- rf source 2
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-- result and status --
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-- result and status --
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res_o => cp_result(3), -- operation result
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res_o => cp_result(3), -- operation result
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fflags_o => fpu_flags_o, -- exception flags
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fflags_o => fpu_flags_o, -- exception flags
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