| Line 139... |
Line 139... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- less than (x < y) --
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-- less than (x < y) --
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opy <= (opc(opc'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
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cmp_opy <= (opc(opc'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opc;
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cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
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cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy));
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cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a less
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cmp_less <= cmp_sub(cmp_sub'left); -- carry (borrow) indicates a "less"
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sub_res <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
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sub_res <= cmp_sub(data_width_c-1 downto 0); -- use the less-comparator also for SUB operations
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|
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-- equal (x = y) --
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-- equal (x = y) --
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cmp_equal <= '1' when (rs1_i = opc) else '0';
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cmp_equal <= '1' when (rs1_i = opc) else '0';
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| Line 168... |
Line 168... |
shift_cmd_ff <= '0';
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shift_cmd_ff <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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shift_cmd_ff <= shift_cmd;
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shift_cmd_ff <= shift_cmd;
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if (shift_start = '1') then -- trigger new shift
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if (shift_start = '1') then -- trigger new shift
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shift_sreg <= opa; -- shift operand
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shift_sreg <= opa; -- shift operand
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shift_cnt <= opb(4 downto 0); -- shift amount
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shift_cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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elsif (shift_run = '1') then -- running shift
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elsif (shift_run = '1') then -- running shift
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shift_cnt <= std_ulogic_vector(unsigned(shift_cnt) - 1);
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shift_cnt <= std_ulogic_vector(unsigned(shift_cnt) - 1);
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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shift_sreg <= shift_sreg(shift_sreg'left-1 downto 0) & '0';
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shift_sreg <= shift_sreg(shift_sreg'left-1 downto 0) & '0';
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else -- SRL: shift right logical / SRA: shift right arithmetical
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else -- SRL: shift right logical / SRA: shift right arithmetical
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| Line 185... |
Line 185... |
-- is shift operation? --
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-- is shift operation? --
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shift_cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0';
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shift_cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0';
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shift_start <= '1' when (shift_cmd = '1') and (shift_cmd_ff = '0') else '0';
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shift_start <= '1' when (shift_cmd = '1') and (shift_cmd_ff = '0') else '0';
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|
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-- shift operation running? --
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-- shift operation running? --
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shift_run <= '1' when (shift_cnt /= "00000") or (shift_start = '1') else '0';
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shift_run <= '1' when (or_all_f(shift_cnt) = '1') or (shift_start = '1') else '0';
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-- Coprocessor Interface ------------------------------------------------------------------
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-- Coprocessor Interface ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cp_interface: process(rstn_i, clk_i)
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cp_interface: process(rstn_i, clk_i)
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| Line 198... |
Line 198... |
cp_cmd_ff <= '0';
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cp_cmd_ff <= '0';
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cp_busy <= '0';
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cp_busy <= '0';
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cp_rb_ff0 <= '0';
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cp_rb_ff0 <= '0';
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cp_rb_ff1 <= '0';
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cp_rb_ff1 <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (ctrl_i(ctrl_sys_m_ext_en_c) = '1') then
|
if (ctrl_i(ctrl_sys_m_ext_en_c) = '1') then -- FIXME add second cp (floating point stuff?)
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cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);
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cp_cmd_ff <= ctrl_i(ctrl_cp_use_c);
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cp_rb_ff0 <= '0';
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cp_rb_ff0 <= '0';
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cp_rb_ff1 <= cp_rb_ff0;
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cp_rb_ff1 <= cp_rb_ff0;
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if (cp_start = '1') then
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if (cp_start = '1') then
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cp_busy <= '1';
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cp_busy <= '1';
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| Line 229... |
Line 229... |
-- ALU Function Select --------------------------------------------------------------------
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-- ALU Function Select --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shift_sreg)
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alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shift_sreg)
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begin
|
begin
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case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
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case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
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when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modification only)
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when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modifications only)
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when alu_cmd_sub_c => alu_res <= sub_res;
|
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when alu_cmd_add_c => alu_res <= add_res;
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when alu_cmd_xor_c => alu_res <= opa xor opb;
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when alu_cmd_xor_c => alu_res <= opa xor opb;
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when alu_cmd_or_c => alu_res <= opa or opb;
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when alu_cmd_or_c => alu_res <= opa or opb;
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when alu_cmd_and_c => alu_res <= opa and opb;
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when alu_cmd_and_c => alu_res <= opa and opb;
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when alu_cmd_sub_c => alu_res <= sub_res;
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when alu_cmd_add_c => alu_res <= add_res;
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when alu_cmd_shift_c => alu_res <= shift_sreg;
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when alu_cmd_shift_c => alu_res <= shift_sreg;
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when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less;
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when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less;
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when others => alu_res <= (others => '0'); -- undefined
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when others => alu_res <= (others => '0'); -- undefined
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end case;
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end case;
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end process alu_function_mux;
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end process alu_function_mux;
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