| Line 1... |
Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Bus Interface Unit >> #
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-- # << NEORV32 - Bus Interface Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # This unit connects the CPU to the memory/IO system. #
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-- # Instruction and data bus interfaces. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 49... |
Line 49... |
port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- cpu instruction fetch interface --
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wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- data output --
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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--
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ma_instr_o : out std_ulogic; -- misaligned instruction address
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be_instr_o : out std_ulogic; -- bus error on instruction access
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-- cpu data access interface --
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addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
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wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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-- status --
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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ma_instr_o : out std_ulogic; -- misaligned instruction address
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d_wait_o : out std_ulogic; -- wait for access to complete
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--
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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-- instruction bus --
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bus_busy_o : out std_ulogic; -- bus unit is busy
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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-- bus system --
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_we_o : out std_ulogic; -- write enable
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_re_o : out std_ulogic; -- read enable
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bus_we_o : out std_ulogic; -- write enable
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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bus_re_o : out std_ulogic; -- read enable
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_err_i : in std_ulogic; -- bus transfer error
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_fence_o : out std_ulogic; -- fence operation
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bus_err_i : in std_ulogic -- bus transfer error
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-- data bus --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_fence_o : out std_ulogic -- fence operation
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);
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);
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end neorv32_cpu_bus;
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end neorv32_cpu_bus;
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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-- interface registers --
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-- data interface registers --
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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|
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-- bus request controller --
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-- data access --
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signal bus_busy : std_ulogic;
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signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
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signal bus_if_req : std_ulogic;
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signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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signal bus_rd_req : std_ulogic;
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signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable
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signal bus_wr_req : std_ulogic;
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signal access_err : std_ulogic;
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signal align_err : std_ulogic;
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signal bus_timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
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-- misaligned access? --
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-- misaligned access? --
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signal misaligned_data, misaligned_instr : std_ulogic;
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signal d_misaligned, i_misaligned : std_ulogic;
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-- bus arbiter --
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type bus_arbiter_t is record
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rd_req : std_ulogic; -- read access in progress
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wr_req : std_ulogic; -- write access in progress
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err_align : std_ulogic; -- alignment error
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err_bus : std_ulogic; -- bus access error
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timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
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end record;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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|
|
begin
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begin
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|
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-- Address and Control --------------------------------------------------------------------
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-- Data Interface: Access Address ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_adr_reg: process(rstn_i, clk_i)
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mem_adr_reg: process(rstn_i, clk_i)
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begin
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begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
|
mar <= alu_i;
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mar <= addr_i;
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end if;
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end if;
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end if;
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end if;
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end process mem_adr_reg;
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end process mem_adr_reg;
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-- address output --
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-- read-back for exception controller --
|
bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch? keep output at PC as long as IF request is active
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mar_o <= mar;
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mar_o <= mar;
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-- write request output --
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-- alignment check --
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bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data);
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misaligned_d_check: process(mar, ctrl_i)
|
|
begin
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-- read request output (also used for instruction fetch) --
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-- check data access --
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bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or (ctrl_i(ctrl_bus_if_c) and (not misaligned_instr)); -- FIXME i_reg and misaligned
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d_misaligned <= '0'; -- default
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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when "00" => -- byte
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d_misaligned <= '0';
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when "01" => -- half-word
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if (mar(0) /= '0') then
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d_misaligned <= '1';
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end if;
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when others => -- word
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if (mar(1 downto 0) /= "00") then
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d_misaligned <= '1';
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end if;
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end case;
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end process misaligned_d_check;
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-- Write Data -----------------------------------------------------------------------------
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-- Data Interface: Write Data -------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_do_reg: process(clk_i)
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mem_do_reg: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then
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if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then
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| Line 136... |
Line 167... |
-- byte enable and output data alignment --
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-- byte enable and output data alignment --
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byte_enable: process(mar, mdo, ctrl_i)
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byte_enable: process(mar, mdo, ctrl_i)
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begin
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begin
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
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when "00" => -- byte
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when "00" => -- byte
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bus_wdata_o(07 downto 00) <= mdo(07 downto 00);
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d_bus_wdata(07 downto 00) <= mdo(07 downto 00);
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bus_wdata_o(15 downto 08) <= mdo(07 downto 00);
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d_bus_wdata(15 downto 08) <= mdo(07 downto 00);
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bus_wdata_o(23 downto 16) <= mdo(07 downto 00);
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d_bus_wdata(23 downto 16) <= mdo(07 downto 00);
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bus_wdata_o(31 downto 24) <= mdo(07 downto 00);
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d_bus_wdata(31 downto 24) <= mdo(07 downto 00);
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bus_ben_o <= (others => '0');
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d_bus_ben <= (others => '0');
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bus_ben_o(to_integer(unsigned(mar(1 downto 0)))) <= '1';
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d_bus_ben(to_integer(unsigned(mar(1 downto 0)))) <= '1';
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when "01" => -- half-word
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when "01" => -- half-word
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bus_wdata_o(31 downto 16) <= mdo(15 downto 00);
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d_bus_wdata(31 downto 16) <= mdo(15 downto 00);
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bus_wdata_o(15 downto 00) <= mdo(15 downto 00);
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d_bus_wdata(15 downto 00) <= mdo(15 downto 00);
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if (mar(1) = '0') then
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if (mar(1) = '0') then
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bus_ben_o <= "0011"; -- low half-word
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d_bus_ben <= "0011"; -- low half-word
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else
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else
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bus_ben_o <= "1100"; -- high half-word
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d_bus_ben <= "1100"; -- high half-word
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end if;
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end if;
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when others => -- word
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when others => -- word
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bus_wdata_o <= mdo;
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d_bus_wdata <= mdo;
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bus_ben_o <= "1111"; -- full word
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d_bus_ben <= "1111"; -- full word
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end case;
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end case;
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end process byte_enable;
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end process byte_enable;
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-- Read Data ------------------------------------------------------------------------------
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-- Data Interface: Read Data --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_out_buf: process(clk_i)
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mem_out_buf: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
-- memory data in register (MDI) --
|
-- memory data in register (MDI) --
|
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
|
mdi <= bus_rdata_i;
|
mdi <= d_bus_rdata;
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end if;
|
end if;
|
end if;
|
end if;
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end process mem_out_buf;
|
end process mem_out_buf;
|
|
|
-- instruction output --
|
-- input data alignment and sign extension --
|
instr_o <= bus_rdata_i;
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|
|
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-- input data align and sign extension --
|
|
read_align: process(mdi, mar, ctrl_i)
|
read_align: process(mdi, mar, ctrl_i)
|
variable signed_v : std_ulogic;
|
variable signed_v : std_ulogic;
|
begin
|
begin
|
signed_v := not ctrl_i(ctrl_bus_unsigned_c);
|
signed_v := not ctrl_i(ctrl_bus_unsigned_c);
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
| Line 207... |
Line 235... |
rdata_o <= mdi; -- full word
|
rdata_o <= mdi; -- full word
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end case;
|
end case;
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end process read_align;
|
end process read_align;
|
|
|
|
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-- Bus Status Controller ------------------------------------------------------------------
|
-- Instruction Interface: Check for Misaligned Access -------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
bus_ctrl: process(rstn_i, clk_i)
|
misaligned_i_check: process(ctrl_i, fetch_pc_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
-- check instruction access --
|
bus_busy <= '0';
|
i_misaligned <= '0'; -- default
|
bus_if_req <= '0';
|
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
|
bus_rd_req <= '0';
|
i_misaligned <= '0'; -- no alignment exceptions possible
|
bus_wr_req <= '0';
|
else -- 32-bit instruction accesses only
|
access_err <= '0';
|
if (fetch_pc_i(1) = '1') then -- PC(0) is always zero
|
align_err <= '0';
|
i_misaligned <= '1';
|
bus_timeout <= (others => '0');
|
|
elsif rising_edge(clk_i) then
|
|
if (bus_busy = '0') or (ctrl_i(ctrl_bus_reset_c) = '1') then -- wait for new request or reset
|
|
bus_busy <= ctrl_i(ctrl_bus_if_c) or ctrl_i(ctrl_bus_rd_c) or ctrl_i(ctrl_bus_wr_c); -- any request at all?
|
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bus_if_req <= ctrl_i(ctrl_bus_if_c); -- instruction fetch
|
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bus_rd_req <= ctrl_i(ctrl_bus_rd_c); -- store access
|
|
bus_wr_req <= ctrl_i(ctrl_bus_wr_c); -- load access
|
|
bus_timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
|
|
access_err <= '0';
|
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align_err <= '0';
|
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else -- bus transfer in progress
|
|
bus_timeout <= std_ulogic_vector(unsigned(bus_timeout) - 1);
|
|
align_err <= (align_err or misaligned_data or misaligned_instr) and (not ctrl_i(ctrl_bus_exc_ack_c));
|
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access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not ctrl_i(ctrl_bus_exc_ack_c));
|
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if (align_err = '1') or (access_err = '1') then
|
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if (ctrl_i(ctrl_bus_exc_ack_c) = '1') then -- wait for controller to ack exception
|
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bus_if_req <= '0';
|
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bus_rd_req <= '0';
|
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bus_wr_req <= '0';
|
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bus_busy <= '0';
|
|
end if;
|
|
elsif (bus_ack_i = '1') then -- normal termination
|
|
bus_if_req <= '0';
|
|
bus_rd_req <= '0';
|
|
bus_wr_req <= '0';
|
|
bus_busy <= '0';
|
|
end if;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process bus_ctrl;
|
end process misaligned_i_check;
|
|
|
-- output bus access error to controller --
|
|
be_instr_o <= bus_if_req and access_err;
|
|
be_load_o <= bus_rd_req and access_err;
|
|
be_store_o <= bus_wr_req and access_err;
|
|
|
|
-- output alignment error to controller --
|
|
ma_instr_o <= bus_if_req and align_err;
|
|
ma_load_o <= bus_rd_req and align_err;
|
|
ma_store_o <= bus_wr_req and align_err;
|
|
|
|
-- terminate bus access --
|
|
bus_cancel_o <= (bus_busy and (align_err or access_err)) or ctrl_i(ctrl_bus_reset_c);
|
|
|
|
-- wait for bus --
|
|
bus_busy_o <= bus_busy;
|
|
bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack
|
|
|
|
|
|
-- Check for Misaligned Access ------------------------------------------------------------
|
-- Instruction Fetch Arbiter --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
misaligned_d_check: process(mar, ctrl_i)
|
ifetch_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
-- check data access --
|
if (rstn_i = '0') then
|
misaligned_data <= '0'; -- default
|
i_arbiter.rd_req <= '0';
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size
|
i_arbiter.wr_req <= '0';
|
when "00" => -- byte
|
i_arbiter.err_align <= '0';
|
misaligned_data <= '0';
|
i_arbiter.err_bus <= '0';
|
when "01" => -- half-word
|
i_arbiter.timeout <= (others => '0');
|
if (mar(0) /= '0') then
|
elsif rising_edge(clk_i) then
|
misaligned_data <= '1';
|
i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
|
|
|
|
-- instruction fetch request --
|
|
if (i_arbiter.rd_req = '0') then -- idle
|
|
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
|
|
i_arbiter.err_align <= i_misaligned;
|
|
i_arbiter.err_bus <= '0';
|
|
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
|
|
else -- in progress
|
|
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
|
|
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
|
|
i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
|
|
if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error?
|
|
if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error
|
|
i_arbiter.rd_req <= '0';
|
end if;
|
end if;
|
when others => -- word
|
elsif (i_bus_ack_i = '1') then -- wait for normal termination
|
if (mar(1 downto 0) /= "00") then
|
i_arbiter.rd_req <= '0';
|
misaligned_data <= '1';
|
|
end if;
|
end if;
|
end case;
|
end if;
|
end process misaligned_d_check;
|
|
|
-- cancel bus access --
|
|
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
|
|
end if;
|
|
end process ifetch_arbiter;
|
|
|
misaligned_i_check: process(ctrl_i, pc_i)
|
|
|
-- wait for bus transaction to finish --
|
|
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
|
|
|
|
-- output instruction fetch error to controller --
|
|
ma_instr_o <= i_arbiter.err_align;
|
|
be_instr_o <= i_arbiter.err_bus;
|
|
|
|
-- instruction bus (read-only) --
|
|
i_bus_addr_o <= fetch_pc_i;
|
|
i_bus_wdata_o <= (others => '0');
|
|
i_bus_ben_o <= (others => '0');
|
|
i_bus_we_o <= '0';
|
|
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned); -- no actual read when misaligned
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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instr_o <= i_bus_rdata_i;
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-- Data Access Arbiter --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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data_access_arbiter: process(rstn_i, clk_i)
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begin
|
begin
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-- check instruction access --
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if (rstn_i = '0') then
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misaligned_instr <= '0'; -- default
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d_arbiter.rd_req <= '0';
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if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
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d_arbiter.wr_req <= '0';
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misaligned_instr <= '0'; -- no alignment exceptions possible
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d_arbiter.err_align <= '0';
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else -- 32-bit instruction accesses only
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d_arbiter.err_bus <= '0';
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if (pc_i(1) = '1') then -- PC(0) is always zero
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d_arbiter.timeout <= (others => '0');
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misaligned_instr <= '1';
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elsif rising_edge(clk_i) then
|
|
|
|
-- data access request --
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if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
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d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
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d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
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d_arbiter.err_align <= d_misaligned;
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d_arbiter.err_bus <= '0';
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d_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
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else -- in progress
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d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
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d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
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d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
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if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error?
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if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error
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d_arbiter.wr_req <= '0';
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d_arbiter.rd_req <= '0';
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end if;
|
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elsif (d_bus_ack_i = '1') then -- wait for normal termination
|
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d_arbiter.wr_req <= '0';
|
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d_arbiter.rd_req <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process misaligned_i_check;
|
|
|
-- cancel bus access --
|
|
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
|
|
end if;
|
|
end process data_access_arbiter;
|
|
|
|
|
|
-- wait for bus transaction to finish --
|
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
|
|
|
-- output data access error to controller --
|
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
|
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
|
|
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
|
|
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
|
|
|
|
-- data bus --
|
|
d_bus_addr_o <= mar;
|
|
d_bus_wdata_o <= d_bus_wdata;
|
|
d_bus_ben_o <= d_bus_ben;
|
|
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned); -- no actual write when misaligned
|
|
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned); -- no actual read when misaligned
|
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
|
d_bus_rdata <= d_bus_rdata_i;
|
|
|
|
|
end neorv32_cpu_bus_rtl;
|
end neorv32_cpu_bus_rtl;
|
|
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No newline at end of file
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No newline at end of file
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