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Line 42... |
use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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Line 111... |
type bus_arbiter_t is record
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type bus_arbiter_t is record
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rd_req : std_ulogic; -- read access in progress
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rd_req : std_ulogic; -- read access in progress
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wr_req : std_ulogic; -- write access in progress
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wr_req : std_ulogic; -- write access in progress
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err_align : std_ulogic; -- alignment error
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err_align : std_ulogic; -- alignment error
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err_bus : std_ulogic; -- bus access error
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err_bus : std_ulogic; -- bus access error
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timeout : std_ulogic_vector(index_size_f(MEM_EXT_TIMEOUT)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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end record;
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end record;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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begin
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begin
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-- instruction fetch request --
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-- instruction fetch request --
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if (i_arbiter.rd_req = '0') then -- idle
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if (i_arbiter.rd_req = '0') then -- idle
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i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
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i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
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i_arbiter.err_align <= i_misaligned;
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i_arbiter.err_align <= i_misaligned;
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i_arbiter.err_bus <= '0';
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i_arbiter.err_bus <= '0';
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i_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
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i_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
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else -- in progress
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else -- in progress
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i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
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i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
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i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error?
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if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error?
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Line 324... |
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
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if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
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d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
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d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
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d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
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d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
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d_arbiter.err_align <= d_misaligned;
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d_arbiter.err_align <= d_misaligned;
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d_arbiter.err_bus <= '0';
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d_arbiter.err_bus <= '0';
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d_arbiter.timeout <= std_ulogic_vector(to_unsigned(MEM_EXT_TIMEOUT, index_size_f(MEM_EXT_TIMEOUT)));
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d_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
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else -- in progress
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else -- in progress
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d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
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d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
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d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
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d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
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d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
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d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
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if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error?
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if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error?
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