| Line 50... |
Line 50... |
PMP_GRANULARITY : natural := 16 -- granularity (1=8B, 2=16B, 3=32B, ...)
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PMP_GRANULARITY : natural := 16 -- granularity (1=8B, 2=16B, 3=32B, ...)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- cpu instruction fetch interface --
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-- cpu instruction fetch interface --
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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i_wait_o : out std_ulogic; -- wait for fetch to complete
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| Line 287... |
Line 288... |
end process misaligned_i_check;
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end process misaligned_i_check;
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|
|
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ifetch_arbiter: process(clk_i)
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ifetch_arbiter: process(rstn_i, clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if (rstn_i = '0') then
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i_arbiter.rd_req <= '0';
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i_arbiter.err_align <= '0';
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i_arbiter.err_bus <= '0';
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i_arbiter.timeout <= (others => '0');
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elsif rising_edge(clk_i) then
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-- instruction fetch request --
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-- instruction fetch request --
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if (i_arbiter.rd_req = '0') then -- idle
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if (i_arbiter.rd_req = '0') then -- idle
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i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
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i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
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i_arbiter.err_align <= i_misaligned;
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i_arbiter.err_align <= i_misaligned;
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i_arbiter.err_bus <= '0';
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i_arbiter.err_bus <= '0';
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| Line 331... |
Line 337... |
instr_o <= i_bus_rdata_i;
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instr_o <= i_bus_rdata_i;
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|
|
|
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-- Data Access Arbiter --------------------------------------------------------------------
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-- Data Access Arbiter --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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data_access_arbiter: process(clk_i)
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data_access_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if (rstn_i = '0') then
|
|
d_arbiter.wr_req <= '0';
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d_arbiter.rd_req <= '0';
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d_arbiter.err_align <= '0';
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d_arbiter.err_bus <= '0';
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d_arbiter.timeout <= (others => '0');
|
|
elsif rising_edge(clk_i) then
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-- data access request --
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-- data access request --
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if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
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if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
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d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
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d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
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d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
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d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
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d_arbiter.err_align <= d_misaligned;
|
d_arbiter.err_align <= d_misaligned;
|
