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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Bus Timeout --
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-- Bus Timeout --
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wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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d_wait_o : out std_ulogic; -- wait for access to complete
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d_wait_o : out std_ulogic; -- wait for access to complete
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--
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--
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bus_excl_ok_o : out std_ulogic; -- bus exclusive access successful
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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-- physical memory protection --
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-- physical memory protection --
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- fence operation
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i_bus_fence_o : out std_ulogic; -- fence operation
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i_bus_lock_o : out std_ulogic; -- locked/exclusive access
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-- data bus --
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-- data bus --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- fence operation
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d_bus_fence_o : out std_ulogic; -- fence operation
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d_bus_lock_o : out std_ulogic -- locked/exclusive access
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d_bus_excl_o : out std_ulogic; -- exclusive access request
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d_bus_excl_i : in std_ulogic -- state of exclusiv access (set if success)
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);
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);
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end neorv32_cpu_bus;
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end neorv32_cpu_bus;
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
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d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
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d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we;
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d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we;
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d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
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d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
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d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
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d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
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d_bus_rdata <= d_bus_rdata_i;
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d_bus_rdata <= d_bus_rdata_i;
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d_bus_lock_o <= ctrl_i(ctrl_bus_lock_c);
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d_bus_excl_o <= ctrl_i(ctrl_bus_excl_c);
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-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
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-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
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pmp_dbus_buffer: process(rstn_i, clk_i)
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pmp_dbus_buffer: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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d_bus_we_buf <= d_bus_we;
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d_bus_we_buf <= d_bus_we;
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d_bus_re_buf <= d_bus_re;
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d_bus_re_buf <= d_bus_re;
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end if;
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end if;
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end process pmp_dbus_buffer;
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end process pmp_dbus_buffer;
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-- Atomic memory access - status buffer --
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atomic_access_status: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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bus_excl_ok_o <= '0';
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elsif rising_edge(clk_i) then
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if (CPU_EXTENSION_RISCV_A = true) then
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if (d_bus_ack_i = '1') then
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bus_excl_ok_o <= d_bus_excl_i; -- set if access was exclusive
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elsif (d_arbiter.rd_req = '0') and (d_arbiter.wr_req = '0') then -- bus access done
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bus_excl_ok_o <= '0';
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end if;
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else
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bus_excl_ok_o <= '0';
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end if;
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end if;
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end process atomic_access_status;
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ifetch_arbiter: process(rstn_i, clk_i)
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ifetch_arbiter: process(rstn_i, clk_i)
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begin
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begin
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i_bus_we_o <= '0';
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i_bus_we_o <= '0';
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i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re;
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i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re;
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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instr_o <= i_bus_rdata_i;
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instr_o <= i_bus_rdata_i;
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i_bus_lock_o <= '0'; -- instruction fetch cannot be atomic
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-- check instruction access --
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-- check instruction access --
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i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
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i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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