| Line 177... |
Line 177... |
assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " & integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) & "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning;
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assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " & integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) & "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning;
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-- Data Interface: Access Address ---------------------------------------------------------
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-- Data Interface: Access Address ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_adr_reg: process(clk_i)
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mem_adr_reg: process(rstn_i, clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if (rstn_i = '0') then
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mar <= (others => def_rst_val_c);
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elsif rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
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if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
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mar <= addr_i;
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mar <= addr_i;
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end if;
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end if;
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end if;
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end if;
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end process mem_adr_reg;
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end process mem_adr_reg;
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| Line 211... |
Line 213... |
end process misaligned_d_check;
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end process misaligned_d_check;
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-- Data Interface: Write Data -------------------------------------------------------------
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-- Data Interface: Write Data -------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_do_reg: process(clk_i)
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mem_do_reg: process(rstn_i, clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if (rstn_i = '0') then
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mdo <= (others => def_rst_val_c);
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elsif rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
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if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
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mdo <= wdata_i; -- memory data output register (MDO)
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mdo <= wdata_i; -- memory data output register (MDO)
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end if;
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end if;
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end if;
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end if;
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end process mem_do_reg;
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end process mem_do_reg;
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| Line 252... |
Line 256... |
end process byte_enable;
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end process byte_enable;
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-- Data Interface: Read Data --------------------------------------------------------------
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-- Data Interface: Read Data --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_out_buf: process(clk_i)
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mem_out_buf: process(rstn_i, clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if (rstn_i = '0') then
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mdi <= (others => def_rst_val_c);
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elsif rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
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if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
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mdi <= d_bus_rdata; -- memory data input register (MDI)
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mdi <= d_bus_rdata; -- memory data input register (MDI)
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end if;
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end if;
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end if;
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end if;
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end process mem_out_buf;
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end process mem_out_buf;
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| Line 440... |
Line 446... |
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- compute address masks (ITERATIVE!!!) --
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-- compute address masks (ITERATIVE!!!) --
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pmp_masks: process(clk_i)
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pmp_masks: process(rstn_i, clk_i)
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begin
|
begin
|
if rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
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if (rstn_i = '0') then
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pmp.addr_mask <= (others => (others => def_rst_val_c));
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elsif rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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pmp.addr_mask(r) <= (others => '0');
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pmp.addr_mask(r) <= (others => '0');
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for i in pmp_g_c to data_width_c-1 loop
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for i in pmp_g_c to data_width_c-1 loop
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pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
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pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
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end loop; -- i
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end loop; -- i
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