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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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bus_busy_o : out std_ulogic; -- bus unit is busy
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exc_ack_i : in std_ulogic; -- exception controller ACK
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exc_ack_i : in std_ulogic; -- exception controller ACK
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-- bus system --
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-- bus system --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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end if;
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end if;
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end if;
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end if;
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end process mem_adr_reg;
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end process mem_adr_reg;
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-- address output --
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-- address output --
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bus_addr_o <= pc_i when (ctrl_i(ctrl_bus_if_c) = '1') else mar; -- is instruction fetch?
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bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch?
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mar_o <= mar;
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mar_o <= mar;
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-- write request output --
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-- write request output --
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bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data);
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bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data);
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-- read request output (also used for instruction fetch) --
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-- read request output (also used for instruction fetch) --
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bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or (ctrl_i(ctrl_bus_if_c) and (not misaligned_instr));
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bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or ((bus_if_req or ctrl_i(ctrl_bus_if_c)) and (not misaligned_instr));
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-- Write Data -----------------------------------------------------------------------------
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-- Write Data -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_do_reg: process(clk_i)
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mem_do_reg: process(clk_i)
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ma_instr_o <= bus_if_req and align_err;
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ma_instr_o <= bus_if_req and align_err;
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ma_load_o <= bus_rd_req and align_err;
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ma_load_o <= bus_rd_req and align_err;
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ma_store_o <= bus_wr_req and align_err;
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ma_store_o <= bus_wr_req and align_err;
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-- wait for bus --
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-- wait for bus --
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bus_busy_o <= bus_busy;
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bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack
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bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack
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-- Check for Misaligned Access ------------------------------------------------------------
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-- Check for Misaligned Access ------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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misaligned_i_check: process(ctrl_i, pc_i)
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misaligned_i_check: process(ctrl_i, pc_i)
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begin
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begin
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-- check instruction access --
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-- check instruction access --
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misaligned_instr <= '0'; -- default
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misaligned_instr <= '0'; -- default
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if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit instruction access only
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if (ctrl_i(ctrl_sys_c_ext_en_c) = '1') then -- 16-bit and 32-bit instruction accesses
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if (pc_i(0) /= '0') then
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misaligned_instr <= '0';
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misaligned_instr <= '1';
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else -- 32-bit instruction accesses only
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end if;
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else -- 32-bit instruction access only
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if (pc_i(1 downto 0) /= "00") then
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if (pc_i(1 downto 0) /= "00") then
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misaligned_instr <= '1';
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misaligned_instr <= '1';
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end if;
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end if;
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end if;
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end if;
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end process misaligned_i_check;
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end process misaligned_i_check;
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