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Line 173... |
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " & integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) & "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning;
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assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " &
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integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) &
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"). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning;
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-- Data Interface: Access Address ---------------------------------------------------------
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-- Data Interface: Access Address ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_adr_reg: process(rstn_i, clk_i)
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mem_adr_reg: process(rstn_i, clk_i)
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-- output reservation status to control unit (to check if SC should write at all) --
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-- output reservation status to control unit (to check if SC should write at all) --
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excl_state_o <= exclusive_lock;
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excl_state_o <= exclusive_lock;
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-- output to memory system --
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-- output to memory system --
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i_bus_lock_o <= '0'; -- instruction fetches cannot be lockes
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i_bus_lock_o <= '0'; -- instruction fetches cannot be locked
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d_bus_lock_o <= exclusive_lock;
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d_bus_lock_o <= exclusive_lock;
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re;
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i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re;
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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instr_o <= i_bus_rdata_i;
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instr_o <= i_bus_rdata_i;
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-- check instruction access --
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-- check instruction access address alignment --
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i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
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i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
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-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
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pmp_ibus_buffer: process(rstn_i, clk_i)
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pmp_ibus_buffer: process(rstn_i, clk_i)
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