| Line 44... |
Line 44... |
use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_control is
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entity neorv32_cpu_control is
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generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.?
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
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-- Memory configuration: Data memory --
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MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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-- Memory configuration: External memory interface --
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MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
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-- Processor peripherals --
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IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- status input --
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-- status input --
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alu_wait_i : in std_ulogic; -- wait for ALU
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alu_wait_i : in std_ulogic; -- wait for ALU
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bus_wait_i : in std_ulogic; -- wait for bus
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bus_i_wait_i : in std_ulogic; -- wait for bus
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bus_d_wait_i : in std_ulogic; -- wait for bus
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-- data input --
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-- data input --
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
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-- data output --
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-- data output --
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| Line 100... |
Line 76... |
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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-- csr data interface --
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-- csr data interface --
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- external interrupt --
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-- external interrupt --
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msw_irq_i : in std_ulogic; -- software interrupt
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- bus access exceptions --
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-- bus access exceptions --
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| Line 111... |
Line 88... |
ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_store_i : in std_ulogic; -- bus error on store data access
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be_store_i : in std_ulogic -- bus error on store data access
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bus_busy_i : in std_ulogic -- bus unit is busy
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);
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);
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end neorv32_cpu_control;
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end neorv32_cpu_control;
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architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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| Line 139... |
Line 115... |
pc_fetch_add : std_ulogic_vector(data_width_c-1 downto 0);
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pc_fetch_add : std_ulogic_vector(data_width_c-1 downto 0);
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ci_return : std_ulogic;
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ci_return : std_ulogic;
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ci_return_nxt : std_ulogic;
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ci_return_nxt : std_ulogic;
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reset : std_ulogic;
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reset : std_ulogic;
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bus_err_ack : std_ulogic;
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bus_err_ack : std_ulogic;
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bus_reset : std_ulogic;
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end record;
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end record;
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signal fetch_engine : fetch_engine_t;
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signal fetch_engine : fetch_engine_t;
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-- pre-decoder --
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-- pre-decoder --
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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| Line 163... |
Line 138... |
clear : std_ulogic;
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clear : std_ulogic;
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end record;
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end record;
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signal ipb : ipb_t;
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signal ipb : ipb_t;
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-- instruction execution engine --
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-- instruction execution engine --
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type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, STORE, LOAD, LOADSTORE_0, LOADSTORE_1, CSR_ACCESS);
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type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS);
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type execute_engine_t is record
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type execute_engine_t is record
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state : execute_engine_state_t;
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state : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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state_prev : execute_engine_state_t;
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i_reg : std_ulogic_vector(31 downto 0);
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i_reg : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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is_ci_nxt : std_ulogic;
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is_ci_nxt : std_ulogic;
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is_jump : std_ulogic; -- current instruction is jump instruction
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is_jump : std_ulogic; -- current instruction is jump instruction
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| Line 184... |
Line 158... |
sleep : std_ulogic; -- CPU in sleep mode
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sleep : std_ulogic; -- CPU in sleep mode
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sleep_nxt : std_ulogic; -- CPU in sleep mode
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sleep_nxt : std_ulogic; -- CPU in sleep mode
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end record;
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end record;
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signal execute_engine : execute_engine_t;
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signal execute_engine : execute_engine_t;
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signal next_pc_tmp : std_ulogic_vector(data_width_c-1 downto 0);
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-- trap controller --
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-- trap controller --
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type trap_ctrl_t is record
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type trap_ctrl_t is record
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exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
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exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
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exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
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exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
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irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
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irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
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irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
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irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
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exc_ack : std_ulogic; -- acknowledge all exceptions
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exc_ack : std_ulogic; -- acknowledge all exceptions
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irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
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irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
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irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
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irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
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cause : std_ulogic_vector(data_width_c-1 downto 0); -- trap ID (for "mcause")
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cause : std_ulogic_vector(4 downto 0); -- trap ID (for "mcause"), only for hw
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cause_nxt : std_ulogic_vector(data_width_c-1 downto 0);
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cause_nxt : std_ulogic_vector(4 downto 0);
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exc_src : std_ulogic_vector(exception_width_c-1 downto 0);
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--
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--
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env_start : std_ulogic; -- start trap handler env
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env_start : std_ulogic; -- start trap handler env
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env_start_ack : std_ulogic; -- start of trap handler acknowledged
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env_start_ack : std_ulogic; -- start of trap handler acknowledged
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env_end : std_ulogic; -- end trap handler env
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env_end : std_ulogic; -- end trap handler env
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--
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--
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| Line 223... |
Line 198... |
we_nxt : std_ulogic;
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we_nxt : std_ulogic;
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re : std_ulogic; -- read enable
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re : std_ulogic; -- read enable
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re_nxt : std_ulogic;
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re_nxt : std_ulogic;
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mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
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mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
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mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)
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mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)
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mip_msip : std_ulogic; -- mip.MSIP: machine software interrupt pending (R/W)
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mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
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mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
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mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
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mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
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mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
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mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
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mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
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mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
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mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
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mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
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mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W)
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mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
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mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
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mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
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mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
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mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
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mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
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mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
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minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
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minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
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mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
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mcycleh : std_ulogic_vector(19 downto 0); -- mcycleh (R/W) - REDUCED BIT-WIDTH!
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minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
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minstreth : std_ulogic_vector(19 downto 0); -- minstreth (R/W) - REDUCED BIT-WIDTH!
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end record;
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end record;
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signal csr : csr_t;
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signal csr : csr_t;
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|
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signal mcycle_msb : std_ulogic;
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signal mcycle_msb : std_ulogic;
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signal minstret_msb : std_ulogic;
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signal minstret_msb : std_ulogic;
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signal systime : std_ulogic_vector(63 downto 0);
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-- illegal instruction check --
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-- illegal instruction check --
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signal illegal_instruction : std_ulogic;
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signal illegal_instruction : std_ulogic;
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signal illegal_register : std_ulogic; -- only for E-extension
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signal illegal_register : std_ulogic; -- only for E-extension
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signal illegal_compressed : std_ulogic; -- only fir C-extension
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signal illegal_compressed : std_ulogic; -- only fir C-extension
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| Line 312... |
Line 287... |
fetch_engine.ci_reg <= fetch_engine.ci_reg_nxt;
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fetch_engine.ci_reg <= fetch_engine.ci_reg_nxt;
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fetch_engine.ci_return <= fetch_engine.ci_return_nxt;
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fetch_engine.ci_return <= fetch_engine.ci_return_nxt;
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end if;
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end if;
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end process fetch_engine_fsm_sync;
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end process fetch_engine_fsm_sync;
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|
|
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-- PC output --
|
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fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0';
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|
|
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-- Fetch Engine FSM Comb ------------------------------------------------------------------
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-- Fetch Engine FSM Comb ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fetch_engine_fsm_comb: process(fetch_engine, execute_engine, csr, ipb, instr_i, bus_wait_i, bus_busy_i, ci_instr32, be_instr_i, ma_instr_i)
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fetch_engine_fsm_comb: process(fetch_engine, csr, ipb, instr_i, bus_i_wait_i, ci_instr32, be_instr_i, ma_instr_i)
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
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fetch_engine.state_nxt <= fetch_engine.state;
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fetch_engine.state_nxt <= fetch_engine.state;
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fetch_engine.pc_fetch_add <= (others => '0');
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fetch_engine.pc_fetch_add <= (others => '0');
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fetch_engine.pc_real_add <= (others => '0');
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fetch_engine.pc_real_add <= (others => '0');
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| Line 328... |
Line 306... |
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf2;
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fetch_engine.i_buf2_nxt <= fetch_engine.i_buf2;
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fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state;
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fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state;
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fetch_engine.ci_reg_nxt <= fetch_engine.ci_reg;
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fetch_engine.ci_reg_nxt <= fetch_engine.ci_reg;
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fetch_engine.ci_return_nxt <= fetch_engine.ci_return;
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fetch_engine.ci_return_nxt <= fetch_engine.ci_return;
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fetch_engine.bus_err_ack <= '0';
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fetch_engine.bus_err_ack <= '0';
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fetch_engine.bus_reset <= '0';
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|
|
|
-- instruction prefetch buffer interface --
|
-- instruction prefetch buffer interface --
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ipb.we <= '0';
|
ipb.we <= '0';
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ipb.clear <= '0';
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ipb.clear <= '0';
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ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
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ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
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| Line 343... |
Line 320... |
|
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when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC
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when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
fetch_engine.i_buf_state_nxt <= (others => '0');
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fetch_engine.i_buf_state_nxt <= (others => '0');
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fetch_engine.ci_return_nxt <= '0';
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fetch_engine.ci_return_nxt <= '0';
|
fetch_engine.bus_reset <= '1'; -- reset bus unit
|
|
ipb.clear <= '1'; -- clear instruction prefetch buffer
|
ipb.clear <= '1'; -- clear instruction prefetch buffer
|
fetch_engine.state_nxt <= IFETCH_0;
|
fetch_engine.state_nxt <= IFETCH_0;
|
|
|
when IFETCH_0 => -- output current PC to bus system, request 32-bit word
|
when IFETCH_0 => -- output current PC to bus system, request 32-bit word
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (bus_busy_i = '0') and (execute_engine.state /= LOAD) and (execute_engine.state /= STORE) and
|
bus_fast_ir <= '1'; -- fast instruction fetch request
|
(execute_engine.state /= LOADSTORE_0) and (execute_engine.state /= LOADSTORE_1) then -- wait if execute engine is using bus unit
|
|
bus_fast_ir <= '1'; -- fast instruction fetch request (output PC to bus.address)
|
|
fetch_engine.state_nxt <= IFETCH_1;
|
fetch_engine.state_nxt <= IFETCH_1;
|
end if;
|
|
|
|
when IFETCH_1 => -- store data from memory to buffer(s)
|
when IFETCH_1 => -- store data from memory to buffer(s)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
|
fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
|
if (bus_wait_i = '0') then -- wait for bus response
|
|
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
|
fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
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fetch_engine.i_buf_state_nxt(1) <= fetch_engine.i_buf_state(0);
|
fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1';
|
|
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them
|
|
if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled?
|
fetch_engine.state_nxt <= IFETCH_2;
|
fetch_engine.state_nxt <= IFETCH_2;
|
|
else
|
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
|
fetch_engine.state_nxt <= IFETCH_0; -- get another instruction word
|
end if;
|
end if;
|
|
|
fetch_engine.i_buf_state_nxt(0) <= '1';
|
|
if (be_instr_i = '1') or (ma_instr_i = '1') then -- any fetch exception?
|
|
fetch_engine.bus_err_ack <= '1'; -- ack bus errors, the execute engine has to take care of them
|
|
end if;
|
end if;
|
|
|
when IFETCH_2 => -- construct instruction and issue
|
when IFETCH_2 => -- construct instruction word and issue
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (fetch_engine.i_buf_state(1) = '1') then
|
|
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
|
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
|
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00);
|
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00);
|
ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
|
ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
|
|
|
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
|
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
|
| Line 383... |
Line 356... |
ipb.we <= '1';
|
ipb.we <= '1';
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
fetch_engine.state_nxt <= IFETCH_0;
|
fetch_engine.state_nxt <= IFETCH_0;
|
end if;
|
end if;
|
|
|
else -- compressed
|
else -- compressed
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
|
fetch_engine.ci_return_nxt <= '1'; -- come back here after issueing
|
fetch_engine.ci_return_nxt <= '1'; -- come back here after issueing
|
fetch_engine.state_nxt <= IFETCH_3;
|
fetch_engine.state_nxt <= IFETCH_3;
|
end if;
|
end if;
|
|
|
else -- 16-bit aligned
|
else -- 16-bit aligned
|
| Line 401... |
Line 372... |
ipb.we <= '1';
|
ipb.we <= '1';
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
fetch_engine.state_nxt <= IFETCH_0;
|
fetch_engine.state_nxt <= IFETCH_0;
|
end if;
|
end if;
|
|
|
else -- compressed
|
else -- compressed
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
|
fetch_engine.ci_return_nxt <= '0'; -- start next fetch after issueing
|
fetch_engine.ci_return_nxt <= '0'; -- start next fetch after issueing
|
fetch_engine.state_nxt <= IFETCH_3;
|
fetch_engine.state_nxt <= IFETCH_3;
|
end if;
|
end if;
|
end if;
|
end if;
|
else
|
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
|
|
fetch_engine.state_nxt <= IFETCH_0;
|
|
end if;
|
|
|
|
when IFETCH_3 => -- additional cycle for issueing decompressed instructions
|
when IFETCH_3 => -- additional cycle for issueing decompressed instructions
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (ipb.free = '1') then -- free entry in buffer?
|
if (ipb.free = '1') then -- free entry in buffer?
|
ipb.we <= '1';
|
ipb.we <= '1';
|
ipb.wdata <= fetch_engine.ci_reg(17 downto 16) & '1' & ci_instr32;
|
ipb.wdata <= fetch_engine.ci_reg(17 downto 16) & '1' & ci_instr32;
|
|
fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
|
if (fetch_engine.ci_return = '0') then
|
if (fetch_engine.ci_return = '0') then
|
fetch_engine.state_nxt <= IFETCH_0;
|
fetch_engine.state_nxt <= IFETCH_0;
|
else
|
else
|
fetch_engine.state_nxt <= IFETCH_2;
|
fetch_engine.state_nxt <= IFETCH_2;
|
| Line 534... |
Line 500... |
end process branch_check;
|
end process branch_check;
|
|
|
|
|
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- for registers that require a specific reset state --
|
-- for registers that DO require a specific reset state --
|
execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
execute_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
if (BOOTLOADER_USE = true) then -- boot from bootloader ROM
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.pc <= boot_base_c(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= boot_base_c(data_width_c-1 downto 1) & '0';
|
|
else -- boot from IMEM
|
|
execute_engine.pc <= MEM_ISPACE_BASE(data_width_c-1 downto 1) & '0';
|
|
execute_engine.last_pc <= MEM_ISPACE_BASE(data_width_c-1 downto 1) & '0';
|
|
end if;
|
|
execute_engine.state <= SYS_WAIT;
|
execute_engine.state <= SYS_WAIT;
|
execute_engine.state_prev <= SYS_WAIT;
|
|
--
|
--
|
execute_engine.sleep <= '0';
|
execute_engine.sleep <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';
|
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
end if;
|
end if;
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.state_prev <= execute_engine.state;
|
|
--
|
--
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
end if;
|
end if;
|
end process execute_engine_fsm_sync_rst;
|
end process execute_engine_fsm_sync_rst;
|
|
|
|
|
-- for registers that DO NOT require a specific reset state --
|
-- for registers that do NOT require a specific reset state --
|
execute_engine_fsm_sync: process(clk_i)
|
execute_engine_fsm_sync: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
| Line 574... |
Line 533... |
-- control signals --
|
-- control signals --
|
ctrl <= ctrl_nxt;
|
ctrl <= ctrl_nxt;
|
end if;
|
end if;
|
end process execute_engine_fsm_sync;
|
end process execute_engine_fsm_sync;
|
|
|
|
|
-- PC output --
|
-- PC output --
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc(data_width_c-1 downto 1) & '0') + 2) when (execute_engine.is_ci = '1') else
|
next_pc_tmp <= std_ulogic_vector(unsigned(execute_engine.pc) + 2) when (execute_engine.is_ci = '1') else std_ulogic_vector(unsigned(execute_engine.pc) + 4);
|
std_ulogic_vector(unsigned(execute_engine.pc(data_width_c-1 downto 1) & '0') + 4);
|
execute_engine.next_pc <= next_pc_tmp(data_width_c-1 downto 1) & '0';
|
fetch_pc_o <= fetch_engine.pc_fetch(data_width_c-1 downto 1) & '0';
|
next_pc_o <= next_pc_tmp(data_width_c-1 downto 1) & '0';
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0';
|
|
|
|
|
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ctrl_output: process(ctrl, execute_engine, fetch_engine, trap_ctrl, csr, bus_fast_ir)
|
ctrl_output: process(ctrl, execute_engine, fetch_engine, trap_ctrl, csr, bus_fast_ir)
|
| Line 592... |
Line 549... |
ctrl_o <= ctrl;
|
ctrl_o <= ctrl;
|
-- direct output of register addresses --
|
-- direct output of register addresses --
|
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
|
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
|
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
|
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
|
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
|
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
|
-- bus access requests --
|
-- fast bus access requests --
|
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir;
|
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir;
|
-- bus control --
|
-- bus error control --
|
ctrl_o(ctrl_bus_exc_ack_c) <= trap_ctrl.env_start_ack or fetch_engine.bus_err_ack;
|
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack;
|
ctrl_o(ctrl_bus_reset_c) <= fetch_engine.bus_reset;
|
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack;
|
end process ctrl_output;
|
end process ctrl_output;
|
|
|
|
|
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
execute_engine_fsm_comb: process(execute_engine, fetch_engine, ipb, trap_ctrl, csr, ctrl,
|
execute_engine_fsm_comb: process(execute_engine, fetch_engine, ipb, trap_ctrl, csr, ctrl,
|
alu_add_i, alu_wait_i, bus_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
|
alu_add_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i)
|
variable alu_immediate_v : std_ulogic;
|
variable alu_immediate_v : std_ulogic;
|
variable alu_operation_v : std_ulogic_vector(2 downto 0);
|
variable alu_operation_v : std_ulogic_vector(2 downto 0);
|
variable rd_is_r0_v : std_ulogic;
|
|
variable rs1_is_r0_v : std_ulogic;
|
variable rs1_is_r0_v : std_ulogic;
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
execute_engine.state_nxt <= execute_engine.state;
|
execute_engine.state_nxt <= execute_engine.state;
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
| Line 637... |
Line 593... |
csr.we_nxt <= '0';
|
csr.we_nxt <= '0';
|
csr.re_nxt <= '0';
|
csr.re_nxt <= '0';
|
|
|
-- control defaults --
|
-- control defaults --
|
ctrl_nxt <= (others => '0'); -- all off at first
|
ctrl_nxt <= (others => '0'); -- all off at first
|
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
|
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
|
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation (SLTIU, SLTU)
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation (SLTIU, SLTU)
|
else -- branches
|
else -- branches
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches (BLTU, BGEU)
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches (BLTU, BGEU)
|
end if;
|
end if;
|
|
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction
|
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction
|
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- arithmetic shift
|
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- arithmetic shift
|
ctrl_nxt(ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- transfer size lsb (00=byte, 01=half-word)
|
ctrl_nxt(ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- transfer size lsb (00=byte, 01=half-word)
|
ctrl_nxt(ctrl_bus_size_msb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- transfer size msb (10=word, 11=?)
|
ctrl_nxt(ctrl_bus_size_msb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- transfer size msb (10=word, 11=?)
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = add
|
|
ctrl_nxt(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); -- CP operation
|
ctrl_nxt(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); -- CP operation
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 implemented yet
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 (MULDIV) implemented yet
|
|
|
-- is immediate operation? --
|
-- is immediate operation? --
|
alu_immediate_v := '0';
|
alu_immediate_v := '0';
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then
|
alu_immediate_v := '1';
|
alu_immediate_v := '1';
|
| Line 675... |
Line 630... |
when funct3_or_c => alu_operation_v := alu_cmd_or_c; -- OR(I)
|
when funct3_or_c => alu_operation_v := alu_cmd_or_c; -- OR(I)
|
when funct3_and_c => alu_operation_v := alu_cmd_and_c; -- AND(I)
|
when funct3_and_c => alu_operation_v := alu_cmd_and_c; -- AND(I)
|
when others => alu_operation_v := (others => '0'); -- undefined
|
when others => alu_operation_v := (others => '0'); -- undefined
|
end case;
|
end case;
|
|
|
-- is rd = r0? --
|
|
rd_is_r0_v := '0';
|
|
if (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") then
|
|
rd_is_r0_v := '1';
|
|
end if;
|
|
|
|
-- is rs1 = r0? --
|
-- is rs1 = r0? --
|
rs1_is_r0_v := '0';
|
rs1_is_r0_v := '0';
|
if (execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
if (execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
rs1_is_r0_v := '1';
|
rs1_is_r0_v := '1';
|
end if;
|
end if;
|
| Line 720... |
Line 669... |
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
if (trap_ctrl.env_start = '1') then
|
if (trap_ctrl.env_start = '1') then
|
trap_ctrl.env_start_ack <= '1';
|
trap_ctrl.env_start_ack <= '1';
|
execute_engine.sleep_nxt <= '0'; -- waky waky
|
execute_engine.sleep_nxt <= '0'; -- waky waky
|
execute_engine.pc_nxt <= csr.mtvec(data_width_c-1 downto 1) & '0';
|
execute_engine.pc_nxt <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- has to be here for wfi to work
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
end if;
|
end if;
|
|
|
when EXECUTE => -- Decode and execute instruction
|
when EXECUTE => -- Decode and execute instruction
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
| Line 738... |
Line 687... |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
-- multi cycle alu operation? --
|
-- multi cycle alu operation? --
|
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation
|
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation
|
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
|
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001")) then -- MULDIV?
|
(execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
else
|
else
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
-- cp access? --
|
-- cp access? --
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV?
|
(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
|
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
|
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- muldiv CP
|
|
end if;
|
end if;
|
|
|
|
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 (only relevant for LUI)
|
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_auipc_c) then -- AUIPC
|
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_auipc_c) then -- AUIPC
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
else -- LUI
|
else -- LUI
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
end if;
|
end if;
|
| Line 773... |
Line 721... |
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation
|
ctrl_nxt(ctrl_bus_mar_we_c) <= '1'; -- write to MAR
|
ctrl_nxt(ctrl_bus_mar_we_c) <= '1'; -- write to MAR
|
ctrl_nxt(ctrl_bus_mdo_we_c) <= '1'; -- write to MDO (only relevant for stores)
|
ctrl_nxt(ctrl_bus_mdo_we_c) <= '1'; -- write to MDO (only relevant for stores)
|
if (fetch_engine.state /= IFETCH_0) then
|
execute_engine.state_nxt <= LOADSTORE_0;
|
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD
|
|
execute_engine.state_nxt <= LOAD;
|
|
else -- STORE
|
|
execute_engine.state_nxt <= STORE;
|
|
end if;
|
|
end if;
|
|
|
|
when opcode_branch_c => -- branch instruction
|
when opcode_branch_c => -- branch instruction
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
| Line 806... |
Line 748... |
execute_engine.is_jump_nxt <= '1'; -- this is a jump operation
|
execute_engine.is_jump_nxt <= '1'; -- this is a jump operation
|
execute_engine.state_nxt <= BRANCH;
|
execute_engine.state_nxt <= BRANCH;
|
|
|
when opcode_fence_c => -- fence operations
|
when opcode_fence_c => -- fence operations
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction (only relevant for fencei)
|
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCEI
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
execute_engine.pc_nxt <= execute_engine.next_pc;
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
execute_engine.state_nxt <= SYS_WAIT;
|
end if;
|
else
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
execute_engine.state_nxt <= DISPATCH;
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
end if;
|
end if;
|
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
|
when opcode_syscsr_c => -- system/csr access
|
when opcode_syscsr_c => -- system/csr access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
|
|
csr.re_nxt <= not rd_is_r0_v; -- only read CSR if not writing to zero_reg
|
|
else
|
|
csr.re_nxt <= '1'; -- always read CSR
|
csr.re_nxt <= '1'; -- always read CSR
|
end if;
|
|
--
|
--
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
when funct12_ecall_c => -- ECALL
|
when funct12_ecall_c => -- ECALL
|
trap_ctrl.env_call <= '1';
|
trap_ctrl.env_call <= '1';
|
| Line 839... |
Line 778... |
execute_engine.sleep_nxt <= '1'; -- good night
|
execute_engine.sleep_nxt <= '1'; -- good night
|
when others => -- undefined
|
when others => -- undefined
|
NULL;
|
NULL;
|
end case;
|
end case;
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
elsif (CPU_EXTENSION_RISCV_Zicsr = true) then -- CSR access
|
|
execute_engine.state_nxt <= CSR_ACCESS;
|
|
else
|
else
|
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then -- CSR access
|
|
execute_engine.state_nxt <= CSR_ACCESS;
|
|
else -- undefined
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
end if;
|
|
|
when others => -- undefined
|
when others => -- undefined
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
|
|
| Line 857... |
Line 798... |
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- default
|
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- default ALU operation = OR
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
-- register operations --
|
-- register operations --
|
when funct3_csrrw_c => -- CSRRW
|
when funct3_csrrw_c => -- CSRRW
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- OPB = rs2
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- OPB = rs2
|
ctrl_nxt(ctrl_rf_clear_rs2_c) <= '1'; -- rs2 = 0
|
ctrl_nxt(ctrl_rf_clear_rs2_c) <= '1'; -- rs2 = 0
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
csr.we_nxt <= '1'; -- always write CSR
|
csr.we_nxt <= '1'; -- always write CSR
|
when funct3_csrrs_c => -- CSRRS
|
when funct3_csrrs_c => -- CSRRS
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = crs1
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if rs1 is not zero_reg
|
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if rs1 is not zero_reg
|
when funct3_csrrc_c => -- CSRRC
|
when funct3_csrrc_c => -- CSRRC
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
|
| Line 880... |
Line 822... |
-- immediate operations --
|
-- immediate operations --
|
when funct3_csrrwi_c => -- CSRRWI
|
when funct3_csrrwi_c => -- CSRRWI
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- rs1 = 0
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- rs1 = 0
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_add_c; -- actual ALU operation = ADD
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
csr.we_nxt <= '1'; -- always write CSR
|
csr.we_nxt <= '1'; -- always write CSR
|
when funct3_csrrsi_c => -- CSRRSI
|
when funct3_csrrsi_c => -- CSRRSI
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
| Line 896... |
Line 838... |
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if UIMM5 is not zero (bits from rs1 filed)
|
csr.we_nxt <= not rs1_is_r0_v; -- write CSR if UIMM5 is not zero (bits from rs1 filed)
|
when others => -- undefined
|
when others => -- undefined
|
NULL;
|
NULL;
|
end case;
|
end case;
|
-- RF write back --
|
-- RF write back --
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output register
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
|
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
|
|
|
when ALU_WAIT => -- wait for multi-cycle ALU operation to finish
|
when ALU_WAIT => -- wait for multi-cycle ALU operation to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (write back all the time)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
|
if (alu_wait_i = '0') then
|
if (alu_wait_i = '0') then
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
when BRANCH => -- update PC for taken branches and jumps
|
when BRANCH => -- update PC for taken branches and jumps
|
| Line 919... |
Line 861... |
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
else
|
else
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
when LOAD => -- trigger memory read request
|
when LOADSTORE_0 => -- trigger memory request
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- fast read request
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD
|
execute_engine.state_nxt <= LOADSTORE_0;
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
|
else -- STORE
|
when STORE => -- trigger memory write request
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request
|
-- ------------------------------------------------------------
|
end if;
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- fast write request
|
execute_engine.state_nxt <= LOADSTORE_1;
|
execute_engine.state_nxt <= LOADSTORE_0;
|
|
|
|
when LOADSTORE_0 => -- memory latency
|
when LOADSTORE_1 => -- memory latency
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD)
|
execute_engine.state_nxt <= LOADSTORE_1;
|
execute_engine.state_nxt <= LOADSTORE_2;
|
|
|
when LOADSTORE_1 => -- wait for bus transaction to finish
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD)
|
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception
|
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
elsif (bus_wait_i = '0') then -- wait here for bus to finish transaction
|
elsif (bus_d_wait_i = '0') then -- wait here for bus to finish transaction
|
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD?
|
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD?
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
end if;
|
end if;
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
| Line 1073... |
Line 1014... |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"341") or -- mepc
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"341") or -- mepc
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"342") or -- mcause
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"342") or -- mcause
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"343") or -- mtval
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"343") or -- mtval
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"344") or -- mip
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"344") or -- mip
|
--
|
--
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycle
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CSR_COUNTERS_USE = true)) or -- cycle
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (IO_MTIME_USE = true)) or -- time
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (CSR_COUNTERS_USE = true)) or -- time
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instret
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CSR_COUNTERS_USE = true)) or -- instret
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycleh
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CSR_COUNTERS_USE = true)) or -- cycleh
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (IO_MTIME_USE = true)) or -- timeh
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (CSR_COUNTERS_USE = true)) or -- timeh
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instreth
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CSR_COUNTERS_USE = true)) or -- instreth
|
--
|
--
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- mcycle
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CSR_COUNTERS_USE = true)) or -- mcycle
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b02") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- minstret
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b02") and (CSR_COUNTERS_USE = true)) or -- minstret
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b80") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- mcycleh
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b80") and (CSR_COUNTERS_USE = true)) or -- mcycleh
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b82") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- minstreth
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b82") and (CSR_COUNTERS_USE = true)) or -- minstreth
|
--
|
--
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f11") or -- mvendorid
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f12") or -- marchid
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f13") or -- mimpid
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f13") or -- mimpid
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f14") or -- mhartid
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"f14") then -- mhartid
|
--
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc0") or -- mfeatures
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc1") or -- mclock
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc4") or -- mispacebase
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc5") or -- mispacesize
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc6") or -- mdspacebase
|
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"fc7") then -- mdspacesize
|
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
|
| Line 1117... |
Line 1053... |
end if;
|
end if;
|
|
|
when others => -- compressed instruction or undefined instruction
|
when others => -- compressed instruction or undefined instruction
|
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode
|
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
else -- compressed instruction: illegal or disabled / not implemented
|
else -- compressed instruction: illegal or not implemented
|
illegal_compressed <= ci_illegal;
|
illegal_compressed <= ci_illegal;
|
end if;
|
end if;
|
|
|
end case;
|
end case;
|
else
|
else
|
| Line 1148... |
Line 1084... |
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.cause <= (others => '0');
|
trap_ctrl.cause <= (others => '0');
|
trap_ctrl.exc_src <= (others => '0');
|
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
-- exception buffer: misaligned load/store/instruction address
|
-- exception buffer: misaligned load/store/instruction address
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
| Line 1165... |
Line 1100... |
-- exception buffer: illegal instruction / env call / break point
|
-- exception buffer: illegal instruction / env call / break point
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or trap_ctrl.env_call) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or trap_ctrl.env_call) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
-- interrupt buffer: machine software/external/timer interrupt
|
-- interrupt buffer: machine software/external/timer interrupt
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or csr.mip_msip) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or clic_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or clic_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
|
|
|
-- trap control --
|
-- trap control --
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program
|
trap_ctrl.exc_src <= trap_ctrl.exc_buf; -- capture exception source for hardware
|
|
trap_ctrl.exc_ack <= '1'; -- clear execption
|
trap_ctrl.exc_ack <= '1'; -- clear execption
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
|
trap_ctrl.env_start <= '1'; -- now we want to start the trap handler
|
trap_ctrl.env_start <= '1'; -- now we want to start the trap handler
|
end if;
|
end if;
|
else -- trap waiting to get started
|
else -- trap waiting to get started
|
| Line 1204... |
Line 1138... |
-- defaults --
|
-- defaults --
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
|
|
-- the following traps are caused by asynchronous exceptions (-> interrupts)
|
-- the following traps are caused by asynchronous exceptions (-> interrupts)
|
-- here we do need an acknowledge mask since several sources can trigger at once
|
-- here we do need a specific acknowledge mask since several sources can trigger at once
|
|
|
-- interrupt: 1.11 machine external interrupt --
|
-- interrupt: 1.11 machine external interrupt --
|
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '1';
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "1011";
|
|
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
|
|
-- interrupt: 1.7 machine timer interrupt --
|
-- interrupt: 1.7 machine timer interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '1';
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0111";
|
|
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
|
|
-- interrupt: 1.3 machine SW interrupt --
|
-- interrupt: 1.3 machine SW interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '1';
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0011";
|
|
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
|
|
|
|
-- the following traps are caused by synchronous exceptions
|
-- the following traps are caused by synchronous exceptions
|
-- here we do not need an acknowledge mask since only one exception (the one
|
-- here we do not need a specific acknowledge mask since only one exception (the one
|
-- with highest priority) can trigger at once
|
-- with highest priority) can trigger at once
|
|
|
-- trap/fault: 0.0 instruction address misaligned --
|
|
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
|
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
|
trap_ctrl.cause_nxt(3 downto 0) <= "0000";
|
|
|
|
-- trap/fault: 0.1 instruction access fault --
|
-- trap/fault: 0.1 instruction access fault --
|
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
trap_ctrl.cause_nxt <= trap_iba_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0001";
|
|
|
|
-- trap/fault: 0.2 illegal instruction --
|
-- trap/fault: 0.2 illegal instruction --
|
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
trap_ctrl.cause_nxt <= trap_iil_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0010";
|
|
|
-- trap/fault: 0.0 instruction address misaligned --
|
|
elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_ima_c;
|
|
|
|
|
-- trap/fault: 0.11 environment call from M-mode --
|
-- trap/fault: 0.11 environment call from M-mode --
|
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
trap_ctrl.cause_nxt <= trap_env_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "1011";
|
|
|
|
-- trap/fault: 0.3 breakpoint --
|
-- trap/fault: 0.3 breakpoint --
|
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
trap_ctrl.cause_nxt <= trap_brk_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0011";
|
|
|
|
|
|
-- trap/fault: 0.6 store address misaligned -
|
-- trap/fault: 0.6 store address misaligned -
|
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
trap_ctrl.cause_nxt <= trap_sma_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0110";
|
|
|
|
-- trap/fault: 0.4 load address misaligned --
|
-- trap/fault: 0.4 load address misaligned --
|
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
trap_ctrl.cause_nxt <= trap_lma_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0100";
|
|
|
|
-- trap/fault: 0.7 store access fault --
|
-- trap/fault: 0.7 store access fault --
|
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
trap_ctrl.cause_nxt <= trap_sbe_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0111";
|
|
|
|
-- trap/fault: 0.5 load access fault --
|
-- trap/fault: 0.5 load access fault --
|
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
trap_ctrl.cause_nxt(data_width_c-1) <= '0';
|
trap_ctrl.cause_nxt <= trap_lbe_c;
|
trap_ctrl.cause_nxt(3 downto 0) <= "0101";
|
|
|
|
-- undefined / not implemented --
|
-- undefined / not implemented --
|
else
|
else
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.cause_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
trap_ctrl.irq_ack_nxt <= (others => '0');
|
| Line 1302... |
Line 1224... |
csr.mstatus_mpie <= '0';
|
csr.mstatus_mpie <= '0';
|
csr.mie_msie <= '0';
|
csr.mie_msie <= '0';
|
csr.mie_meie <= '0';
|
csr.mie_meie <= '0';
|
csr.mie_mtie <= '0';
|
csr.mie_mtie <= '0';
|
csr.mtvec <= (others => '0');
|
csr.mtvec <= (others => '0');
|
csr.mtval <= (others => '0');
|
csr.mscratch <= (others => '0');
|
csr.mepc <= (others => '0');
|
csr.mepc <= (others => '0');
|
csr.mip_msip <= '0';
|
csr.mcause <= (others => '0');
|
|
csr.mtval <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
-- access --
|
-- access --
|
csr.we <= csr.we_nxt;
|
csr.we <= csr.we_nxt;
|
csr.re <= csr.re_nxt;
|
csr.re <= csr.re_nxt;
|
|
|
-- defaults --
|
|
csr.mip_msip <= '0';
|
|
|
|
-- registers that can be modified by user --
|
-- registers that can be modified by user --
|
if (csr.we = '1') then -- manual update
|
if (csr.we = '1') then -- manual update
|
|
|
-- Machine CSRs: Standard read/write
|
-- Machine CSRs: Standard read/write
|
if (execute_engine.i_reg(31 downto 28) = x"3") then
|
if (execute_engine.i_reg(31 downto 28) = x"3") then
|
| Line 1330... |
Line 1250... |
when x"4" => -- R/W: mie - machine interrupt-enable register
|
when x"4" => -- R/W: mie - machine interrupt-enable register
|
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable
|
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable
|
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable
|
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable
|
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable
|
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable
|
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
csr.mtvec <= csr_wdata_i;
|
csr.mtvec <= csr_wdata_i(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
when others =>
|
when others =>
|
NULL;
|
NULL;
|
end case;
|
end case;
|
end if;
|
end if;
|
-- machine trap handling --
|
-- machine trap handling --
|
if (execute_engine.i_reg(27 downto 24) = x"4") then
|
if (execute_engine.i_reg(27 downto 24) = x"4") then
|
case execute_engine.i_reg(23 downto 20) is
|
case execute_engine.i_reg(23 downto 20) is
|
when x"0" => -- R/W: mscratch - machine scratch register
|
when x"0" => -- R/W: mscratch - machine scratch register
|
csr.mscratch <= csr_wdata_i;
|
csr.mscratch <= csr_wdata_i;
|
when x"1" => -- R/W: mepc - machine exception program counter
|
when x"1" => -- R/W: mepc - machine exception program counter
|
csr.mepc <= csr_wdata_i;
|
csr.mepc <= csr_wdata_i(data_width_c-1 downto 1) & '0';
|
when x"2" => -- R/W: mcause - machine trap cause
|
when x"2" => -- R/W: mcause - machine trap cause
|
csr.mcause <= csr_wdata_i;
|
csr.mcause <= csr_wdata_i;
|
when x"3" => -- R/W: mtval - machine bad address or instruction
|
when x"3" => -- R/W: mtval - machine bad address or instruction
|
csr.mtval <= csr_wdata_i;
|
csr.mtval <= csr_wdata_i;
|
when x"4" => -- R/W: mip - machine interrupt pending
|
|
csr.mip_msip <= csr_wdata_i(03); -- manual SW IRQ trigger
|
|
when others =>
|
when others =>
|
NULL;
|
NULL;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- automatic update by hardware --
|
-- automatic update by hardware --
|
else
|
else
|
|
|
-- machine exception PC & exception value register --
|
-- machine exception PC & trap value register --
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler started?
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
csr.mcause <= trap_ctrl.cause;
|
csr.mcause <= trap_ctrl.cause(4) & "000" & x"000000" & trap_ctrl.cause(3 downto 0);
|
if (csr.mcause(data_width_c-1) = '1') then -- for INTERRUPTS only
|
if (trap_ctrl.cause(4) = '1') then -- for INTERRUPTS only
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
csr.mtval <= (others => '0'); -- mtval not defined for interrupts
|
csr.mtval <= (others => '0'); -- mtval is zero for interrupts
|
else -- for EXCEPTIONS (according to their priority)
|
else -- for EXCEPTIONS (according to their priority)
|
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
if ((trap_ctrl.exc_src(exception_iaccess_c) or trap_ctrl.exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction
|
if (trap_ctrl.cause(3 downto 0) = trap_iba_c(3 downto 0)) or -- instr access error OR
|
|
(trap_ctrl.cause(3 downto 0) = trap_ima_c(3 downto 0)) or -- misaligned instruction OR
|
|
(trap_ctrl.cause(3 downto 0) = trap_brk_c(3 downto 0)) or -- breakpoint OR
|
|
(trap_ctrl.cause(3 downto 0) = trap_env_c(3 downto 0)) then -- env call OR
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
elsif (trap_ctrl.exc_src(exception_iillegal_c) = '1') then -- illegal instruction
|
elsif (trap_ctrl.cause(3 downto 0) = trap_iil_c(3 downto 0)) then -- illegal instruction
|
csr.mtval <= execute_engine.i_reg; -- the faulting instruction itself
|
csr.mtval <= execute_engine.i_reg; -- faulting instruction itself
|
else -- load/store msialignments/access errors
|
else -- load/store misalignments/access errors
|
csr.mtval <= mar_i; -- faulting data access address
|
csr.mtval <= mar_i; -- faulting data access address
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- context switch in mstatus --
|
-- context switch in mstatus --
|
if (trap_ctrl.env_start_ack = '1') then -- actually entering trap
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
csr.mstatus_mie <= '0';
|
csr.mstatus_mie <= '0';
|
if (csr.mstatus_mpie = '0') then -- prevent loosing the prev MIE state in nested traps
|
if (csr.mstatus_mpie = '0') then -- prevent loosing the prev MIE state in nested traps
|
csr.mstatus_mpie <= csr.mstatus_mie;
|
csr.mstatus_mpie <= csr.mstatus_mie;
|
end if;
|
end if;
|
elsif (trap_ctrl.env_end = '1') then -- return from exception
|
elsif (trap_ctrl.env_end = '1') then -- return from exception
|
| Line 1404... |
Line 1325... |
|
|
-- machine trap setup --
|
-- machine trap setup --
|
when x"300" => -- R/W: mstatus - machine status register
|
when x"300" => -- R/W: mstatus - machine status register
|
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE
|
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE
|
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE
|
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE
|
csr_rdata_o(11) <= '1'; -- MPP low
|
csr_rdata_o(11) <= '1'; -- MPP low - M-mode
|
csr_rdata_o(12) <= '1'; -- MPP high
|
csr_rdata_o(12) <= '1'; -- MPP high - M-mode
|
when x"301" => -- R/-: misa - ISA and extensions
|
when x"301" => -- R/-: misa - ISA and extensions
|
csr_rdata_o(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr_rdata_o(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
csr_rdata_o(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
|
csr_rdata_o(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
|
| Line 1419... |
Line 1340... |
when x"304" => -- R/W: mie - machine interrupt-enable register
|
when x"304" => -- R/W: mie - machine interrupt-enable register
|
csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable
|
csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable
|
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable
|
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable
|
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable
|
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable
|
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
csr_rdata_o <= csr.mtvec;
|
csr_rdata_o <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
|
|
-- machine trap handling --
|
-- machine trap handling --
|
when x"340" => -- R/W: mscratch - machine scratch register
|
when x"340" => -- R/W: mscratch - machine scratch register
|
csr_rdata_o <= csr.mscratch;
|
csr_rdata_o <= csr.mscratch;
|
when x"341" => -- R/W: mepc - machine exception program counter
|
when x"341" => -- R/W: mepc - machine exception program counter
|
csr_rdata_o <= csr.mepc;
|
csr_rdata_o <= csr.mepc(data_width_c-1 downto 1) & '0';
|
when x"342" => -- R/W: mcause - machine trap cause
|
when x"342" => -- R/W: mcause - machine trap cause
|
csr_rdata_o <= csr.mcause;
|
csr_rdata_o <= csr.mcause;
|
when x"343" => -- R/W: mtval - machine bad address or instruction
|
when x"343" => -- R/W: mtval - machine bad address or instruction
|
csr_rdata_o <= csr.mtval;
|
csr_rdata_o <= csr.mtval;
|
when x"344" => -- R/W: mip - machine interrupt pending
|
when x"344" => -- R/W: mip - machine interrupt pending
|
| Line 1438... |
Line 1359... |
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
|
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
|
|
|
-- counter and timers --
|
-- counter and timers --
|
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
|
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
|
csr_rdata_o <= csr.mcycle(31 downto 0);
|
csr_rdata_o <= csr.mcycle(31 downto 0);
|
|
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
|
|
csr_rdata_o <= systime(31 downto 0);
|
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW
|
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW
|
csr_rdata_o <= csr.minstret(31 downto 0);
|
csr_rdata_o <= csr.minstret(31 downto 0);
|
when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH
|
when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH
|
csr_rdata_o <= csr.mcycleh;
|
csr_rdata_o <= x"000" & csr.mcycleh(19 downto 0); -- only the lowest 20 bit!
|
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
|
|
csr_rdata_o <= csr.minstreth;
|
|
|
|
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
|
|
csr_rdata_o <= time_i(31 downto 0);
|
|
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
|
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
|
csr_rdata_o <= time_i(63 downto 32);
|
csr_rdata_o <= systime(63 downto 32);
|
|
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
|
|
csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit!
|
|
|
-- machine information registers --
|
-- machine information registers --
|
when x"f13" => -- R/-: mimpid - implementation ID / version
|
when x"f11" => -- R/-: mvendorid
|
|
csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32
|
|
when x"f12" => -- R/-: marchid
|
|
csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32
|
|
when x"f13" => -- R/-: mimpid - implementation ID / NEORV32: version
|
csr_rdata_o <= hw_version_c;
|
csr_rdata_o <= hw_version_c;
|
when x"f14" => -- R/-: mhartid - hardware thread ID
|
when x"f14" => -- R/-: mhartid - hardware thread ID
|
csr_rdata_o <= HART_ID;
|
csr_rdata_o <= HW_THREAD_ID;
|
|
|
-- CUSTOM read-only machine CSRs --
|
|
when x"fc0" => -- R/-: mfeatures - implemented processor devices/features
|
|
csr_rdata_o(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader?
|
|
csr_rdata_o(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface?
|
|
csr_rdata_o(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory?
|
|
csr_rdata_o(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM?
|
|
csr_rdata_o(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory?
|
|
csr_rdata_o(05) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- implement RISC-V (performance) counter?
|
|
--
|
|
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)?
|
|
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)?
|
|
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)?
|
|
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)?
|
|
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)?
|
|
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)?
|
|
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)?
|
|
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)?
|
|
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)?
|
|
csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)?
|
|
when x"fc1" => -- R/-: mclock - processor clock speed
|
|
csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
|
|
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space
|
|
csr_rdata_o <= MEM_ISPACE_BASE;
|
|
when x"fc5" => -- R/-: mdspacebase - Base address of data memory space
|
|
csr_rdata_o <= MEM_DSPACE_BASE;
|
|
when x"fc6" => -- R/-: mispacesize - Total size of instruction memory space in byte
|
|
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32));
|
|
when x"fc7" => -- R/-: mdspacesize - Total size of data memory space in byte
|
|
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32));
|
|
|
|
-- undefined/unavailable --
|
-- undefined/unavailable --
|
when others =>
|
when others =>
|
csr_rdata_o <= (others => '0'); -- not implemented
|
csr_rdata_o <= (others => '0'); -- not implemented
|
|
|
end case;
|
end case;
|
|
else
|
|
csr_rdata_o <= (others => '0');
|
end if;
|
end if;
|
end if;
|
end if;
|
end process csr_read_access;
|
end process csr_read_access;
|
|
|
|
-- time[h] CSR --
|
|
systime <= time_i when (CSR_COUNTERS_USE = true) else (others => '0');
|
|
|
|
|
-- RISC-V Counter CSRs --------------------------------------------------------------------
|
-- RISC-V Counter CSRs --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_counters: process(rstn_i, clk_i)
|
csr_counters: process(rstn_i, clk_i)
|
begin
|
begin
|
| Line 1508... |
Line 1407... |
csr.mcycleh <= (others => '0');
|
csr.mcycleh <= (others => '0');
|
csr.minstreth <= (others => '0');
|
csr.minstreth <= (others => '0');
|
mcycle_msb <= '0';
|
mcycle_msb <= '0';
|
minstret_msb <= '0';
|
minstret_msb <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true) then
|
if (CSR_COUNTERS_USE = true) then
|
|
|
-- mcycle (cycle) --
|
-- mcycle (cycle) --
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access
|
csr.mcycle(31 downto 0) <= csr_wdata_i;
|
csr.mcycle(31 downto 0) <= csr_wdata_i;
|
| Line 1521... |
Line 1420... |
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
end if;
|
end if;
|
|
|
-- mcycleh (cycleh) --
|
-- mcycleh (cycleh) --
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
|
csr.mcycleh <= csr_wdata_i;
|
csr.mcycleh <= csr_wdata_i(19 downto 0);
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
end if;
|
end if;
|
|
|
-- minstret (instret) --
|
-- minstret (instret) --
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
|
csr.minstret(31 downto 0) <= csr_wdata_i;
|
csr.minstret(31 downto 0) <= csr_wdata_i;
|
csr.minstret(32) <= '0';
|
csr.minstret(32) <= '0';
|
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
|
elsif (execute_engine.state_nxt /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
end if;
|
end if;
|
|
|
-- minstreth (instreth) --
|
-- minstreth (instreth) --
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
|
csr.minstreth <= csr_wdata_i;
|
csr.minstreth <= csr_wdata_i(19 downto 0);
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
end if;
|
end if;
|
|
|
|
else -- if not implemented
|
|
csr.mcycle <= (others => '0');
|
|
csr.minstret <= (others => '0');
|
|
csr.mcycleh <= (others => '0');
|
|
csr.minstreth <= (others => '0');
|
|
mcycle_msb <= '0';
|
|
minstret_msb <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process csr_counters;
|
end process csr_counters;
|
|
|
|
|
