| Line 923... |
Line 923... |
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-- Illegal CSR Access Check ---------------------------------------------------------------
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-- Illegal CSR Access Check ---------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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invalid_csr_access_check: process(execute_engine.i_reg, csr.privilege)
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invalid_csr_access_check: process(execute_engine.i_reg, csr.privilege)
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variable is_m_mode_v : std_ulogic;
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variable is_m_mode_v : std_ulogic;
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variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
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-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
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begin
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begin
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-- are we in machine mode? --
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-- are we in machine mode? --
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if (csr.privilege = priv_mode_m_c) then
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if (csr.privilege = priv_mode_m_c) then
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is_m_mode_v := '1';
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is_m_mode_v := '1';
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else
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else
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is_m_mode_v := '0';
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is_m_mode_v := '0';
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end if;
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end if;
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-- is this CSR instruction really going to write/read to/from a CSR? --
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
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csr_wacc_v := '1'; -- always write CSR
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-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
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else
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csr_wacc_v := or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); -- write allowed if rs1/uimm5 != 0
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-- csr_racc_v := '1'; -- always read CSR
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end if;
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-- check CSR access --
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-- check CSR access --
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case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
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case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
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when csr_mstatus_c => csr_acc_valid <= is_m_mode_v;
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when csr_mstatus_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_misa_c => csr_acc_valid <= is_m_mode_v;
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when csr_misa_c => csr_acc_valid <= is_m_mode_v;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only for the NEORV32 but we don't cause an exception here for compatibility
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when csr_mie_c => csr_acc_valid <= is_m_mode_v;
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when csr_mie_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_mtvec_c => csr_acc_valid <= is_m_mode_v;
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when csr_mtvec_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_mscratch_c => csr_acc_valid <= is_m_mode_v;
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when csr_mscratch_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_mepc_c => csr_acc_valid <= is_m_mode_v;
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when csr_mepc_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_mcause_c => csr_acc_valid <= is_m_mode_v;
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when csr_mcause_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_mtval_c => csr_acc_valid <= is_m_mode_v;
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when csr_mtval_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_mip_c => csr_acc_valid <= is_m_mode_v;
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when csr_mip_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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--
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--
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when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v;
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when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v; -- M-mode only
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when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v;
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when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- M-mode only
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--
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--
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when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v;
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when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v; -- M-mode only
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when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 2)) and is_m_mode_v;
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when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 2)) and is_m_mode_v; -- M-mode only
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when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 3)) and is_m_mode_v;
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when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 3)) and is_m_mode_v; -- M-mode only
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when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 4)) and is_m_mode_v;
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when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 4)) and is_m_mode_v; -- M-mode only
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when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v;
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when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- M-mode only
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when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 6)) and is_m_mode_v;
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when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 6)) and is_m_mode_v; -- M-mode only
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when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 7)) and is_m_mode_v;
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when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 7)) and is_m_mode_v; -- M-mode only
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when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 8)) and is_m_mode_v;
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when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 8)) and is_m_mode_v; -- M-mode only
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--
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--
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when csr_mcycle_c => csr_acc_valid <= is_m_mode_v;
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when csr_mcycle_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_minstret_c => csr_acc_valid <= is_m_mode_v;
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when csr_minstret_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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--
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--
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when csr_mcycleh_c => csr_acc_valid <= is_m_mode_v;
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when csr_mcycleh_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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when csr_minstreth_c => csr_acc_valid <= is_m_mode_v;
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when csr_minstreth_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
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--
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--
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when csr_cycle_c => csr_acc_valid <= '1';
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when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
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when csr_time_c => csr_acc_valid <= '1';
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when csr_time_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
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when csr_instret_c => csr_acc_valid <= '1';
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when csr_instret_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
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--
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--
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when csr_cycleh_c => csr_acc_valid <= '1';
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when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
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when csr_timeh_c => csr_acc_valid <= '1';
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when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
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when csr_instreth_c => csr_acc_valid <= '1';
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when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
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--
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--
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when csr_mvendorid_c => csr_acc_valid <= is_m_mode_v;
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when csr_mvendorid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
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when csr_marchid_c => csr_acc_valid <= is_m_mode_v;
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when csr_marchid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
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when csr_mimpid_c => csr_acc_valid <= is_m_mode_v;
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when csr_mimpid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
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when csr_mhartid_c => csr_acc_valid <= is_m_mode_v;
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when csr_mhartid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
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--
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--
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when csr_mzext_c => csr_acc_valid <= is_m_mode_v;
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when csr_mzext_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
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--
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--
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when others => csr_acc_valid <= '0'; -- undefined, invalid access
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when others => csr_acc_valid <= '0'; -- undefined, invalid access
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end case;
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end case;
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end process invalid_csr_access_check;
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end process invalid_csr_access_check;
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Line 1482... |
-- machine trap handling --
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-- machine trap handling --
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if (execute_engine.i_reg(27 downto 24) = csr_mepc_c(7 downto 4)) then
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if (execute_engine.i_reg(27 downto 24) = csr_mepc_c(7 downto 4)) then
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if (execute_engine.i_reg(23 downto 20) = csr_mepc_c(3 downto 0)) then -- R/W: mepc - machine exception program counter
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if (execute_engine.i_reg(23 downto 20) = csr_mepc_c(3 downto 0)) then -- R/W: mepc - machine exception program counter
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csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
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csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
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end if;
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end if;
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if (execute_engine.i_reg(23 downto 20) = csr_mcause_c(3 downto 0)) then -- R/W: mcause - machine trap cause
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csr.mcause <= (others => '0');
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csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
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csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
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end if;
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if (execute_engine.i_reg(23 downto 20) = csr_mtval_c(3 downto 0)) then -- R/W: mtval - machine bad address or instruction
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if (execute_engine.i_reg(23 downto 20) = csr_mtval_c(3 downto 0)) then -- R/W: mtval - machine bad address or instruction
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csr.mtval <= csr.wdata;
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csr.mtval <= csr.wdata;
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end if;
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end if;
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end if;
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end if;
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Line 1521... |
end if;
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end if;
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end if;
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end if;
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-- mstatus: context switch --
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-- mstatus: context switch --
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if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
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if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
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-- trap ID code --
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csr.mcause <= (others => '0');
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csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
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csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
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--
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csr.mstatus_mie <= '0'; -- disable interrupts
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csr.mstatus_mie <= '0'; -- disable interrupts
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csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
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csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
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if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
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if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
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csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
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csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
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csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
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csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
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| Line 1525... |
Line 1547... |
csr.privilege <= priv_mode_m_c;
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csr.privilege <= priv_mode_m_c;
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csr.mstatus_mpp <= priv_mode_m_c;
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csr.mstatus_mpp <= priv_mode_m_c;
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end if;
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end if;
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end if;
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end if;
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-- --------------------------------------------------------------------------------
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-- CSRs that can be written by hardware only
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-- --------------------------------------------------------------------------------
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-- mcause
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if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
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-- trap ID code --
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csr.mcause <= (others => '0');
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csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
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csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
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end if;
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end if;
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end if;
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end process csr_write_access;
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end process csr_write_access;
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-- Control and Status Registers Read Access -----------------------------------------------
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-- Control and Status Registers Read Access -----------------------------------------------
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