| Line 549... |
Line 549... |
end process instruction_buffer_ctrl;
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end process instruction_buffer_ctrl;
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|
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instruction_buffer_data: process(clk_i)
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instruction_buffer_data: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (i_buf.we = '1') and (i_buf.clear = '0') then
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if (i_buf.we = '1') then
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i_buf.rdata <= i_buf.wdata;
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i_buf.rdata <= i_buf.wdata;
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end if;
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end if;
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end if;
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end if;
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end process instruction_buffer_data;
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end process instruction_buffer_data;
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| Line 1533... |
Line 1533... |
if (PMP_NUM_REGIONS >= 1) then
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if (PMP_NUM_REGIONS >= 1) then
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if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg0_c(3 downto 0)) then -- pmpcfg0
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if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg0_c(3 downto 0)) then -- pmpcfg0
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for j in 0 to 3 loop -- bytes in pmpcfg CSR
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for j in 0 to 3 loop -- bytes in pmpcfg CSR
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if ((j+1) <= PMP_NUM_REGIONS) then
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if ((j+1) <= PMP_NUM_REGIONS) then
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if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access
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if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access
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csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R
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csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
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csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W
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csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
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csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X
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csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
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csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
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csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
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csr.pmpcfg(0+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
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csr.pmpcfg(0+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
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csr.pmpcfg(0+j)(5) <= '0'; -- reserved
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csr.pmpcfg(0+j)(5) <= '0'; -- reserved
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csr.pmpcfg(0+j)(6) <= '0'; -- reserved
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csr.pmpcfg(0+j)(6) <= '0'; -- reserved
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csr.pmpcfg(0+j)(7) <= csr.wdata(j*8+7); -- L
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csr.pmpcfg(0+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode)
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end if;
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end if;
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end if;
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end if;
|
end loop; -- j (bytes in CSR)
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end loop; -- j (bytes in CSR)
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end if;
|
end if;
|
end if;
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end if;
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if (PMP_NUM_REGIONS >= 5) then
|
if (PMP_NUM_REGIONS >= 5) then
|
if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg1_c(3 downto 0)) then -- pmpcfg1
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if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg1_c(3 downto 0)) then -- pmpcfg1
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for j in 0 to 3 loop -- bytes in pmpcfg CSR
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for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
if ((j+1+4) <= PMP_NUM_REGIONS) then
|
if ((j+1+4) <= PMP_NUM_REGIONS) then
|
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access
|
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access
|
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R
|
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
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csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W
|
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
|
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X
|
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
|
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(4+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
|
csr.pmpcfg(4+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
|
csr.pmpcfg(4+j)(5) <= '0'; -- reserved
|
csr.pmpcfg(4+j)(5) <= '0'; -- reserved
|
csr.pmpcfg(4+j)(6) <= '0'; -- reserved
|
csr.pmpcfg(4+j)(6) <= '0'; -- reserved
|
csr.pmpcfg(4+j)(7) <= csr.wdata(j*8+7); -- L
|
csr.pmpcfg(4+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode)
|
end if;
|
end if;
|
end if;
|
end if;
|
end loop; -- j (bytes in CSR)
|
end loop; -- j (bytes in CSR)
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 1729... |
Line 1729... |
-- Control and Status Registers Read Access -----------------------------------------------
|
-- Control and Status Registers Read Access -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_read_access: process(clk_i)
|
csr_read_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
csr.rdata <= (others => '0'); -- default
|
|
csr.re <= csr.re_nxt; -- read access?
|
csr.re <= csr.re_nxt; -- read access?
|
|
csr.rdata <= (others => '0'); -- default output
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
|
|
-- machine trap setup --
|
-- machine trap setup --
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
| Line 1766... |
Line 1766... |
-- machine trap handling --
|
-- machine trap handling --
|
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
|
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
|
csr.rdata <= csr.mscratch;
|
csr.rdata <= csr.mscratch;
|
when csr_mepc_c => -- R/W: mepc - machine exception program counter
|
when csr_mepc_c => -- R/W: mepc - machine exception program counter
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
when csr_mcause_c => -- R/-: mcause - machine trap cause
|
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
csr.rdata <= csr.mcause;
|
csr.rdata <= csr.mcause;
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
csr.rdata <= csr.mtval;
|
csr.rdata <= csr.mtval;
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
|
csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
|
