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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Co-Processor: Single-Precision Floating Point Unit (RISC-V "F" Extension) >> #
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-- # << NEORV32 - CPU Co-Processor: Single-Prec. Floating Point Unit (RISC-V "Zfinx" Extension) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # #
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-- # #
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-- # !!! WORK-IN-PROGRESS !!! #
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-- # !!! WORK-IN-PROGRESS !!! #
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-- # !!! THIS UNIT IS NOT FUNCTIONAL YET !!! #
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-- # !!! THIS UNIT IS NOT FUNCTIONAL YET !!! #
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-- # #
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-- # #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # !!! Enabling the F extension does not has an effect on the CPU. If F is enabled, there !!! #
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-- # The Zfinx floating-point extension uses the integer register file (x) for all FP operations. #
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-- # !!! will be no traps when trying to execute floating-point instructions, since the main !!! #
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-- # See the official RISC-V specs (https://github.com/riscv/riscv-zfinx) for more information. #
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-- # !!! CPU control unit allready provides all necessary F-extension infrastructure. !!! #
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-- # ********************************************************************************************* #
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-- # !!! However, all F instructions will always return zero. !!! #
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-- # !! Enabling the Zfinx extension does not has an effect on the CPU. If F is enabled, there !! #
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-- # !! will be no traps when trying to execute floating-point instructions, since the main !! #
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-- # !! CPU control unit allready provides all necessary Zfinx-extension infrastructure. !! #
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-- # !! However, all Zfinx instructions will always return zero. !! #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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start_i : in std_ulogic; -- trigger operation
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start_i : in std_ulogic; -- trigger operation
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-- data input --
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-- data input --
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frm_i : in std_ulogic_vector(2 downto 0); -- rounding mode
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frm_i : in std_ulogic_vector(2 downto 0); -- rounding mode
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reg_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source (rs1)
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read-data
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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-- result and status --
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-- result and status --
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fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
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mem_o : out std_ulogic_vector(data_width_c-1 downto 0); -- memory write-data
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
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valid_o : out std_ulogic -- data output valid
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valid_o : out std_ulogic -- data output valid
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);
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);
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end neorv32_cpu_cp_fpu;
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end neorv32_cpu_cp_fpu;
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architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is
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architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is
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begin
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begin
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-- There is nothing to see here yet -------------------------------------------------------
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-- There is nothing to see here yet -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fflags_o <= (others => '0');
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mem_o <= (others => '0');
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res_o <= (others => '0');
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res_o <= (others => '0');
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fflags_o <= (others => '0');
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valid_o <= start_i;
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valid_o <= start_i;
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end neorv32_cpu_cp_fpu_rtl;
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end neorv32_cpu_cp_fpu_rtl;
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