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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_cp_muldiv.vhd] - Diff between revs 3 and 4
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| Rev 3 |
Rev 4 |
| Line 109... |
Line 109... |
-- FSM --
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-- FSM --
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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opx <= rs1_i;
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opx <= rs1_i;
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opy <= rs2_i;
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opy <= rs2_i;
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if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then
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cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
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cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
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if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then
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state <= DECODE;
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state <= DECODE;
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end if;
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end if;
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when DECODE =>
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when DECODE =>
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cnt <= "11111";
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if (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) then -- result sign compensation for div?
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if (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) then -- result sign compensation for div?
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div_res_corr <= opx(opx'left) xor opy(opy'left);
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div_res_corr <= opx(opx'left) xor opy(opy'left);
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else
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else
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div_res_corr <= '0';
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div_res_corr <= '0';
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end if;
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end if;
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cnt <= "11111";
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if (operation = '1') then -- division
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if (operation = '1') then -- division
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state <= INIT_OPX;
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state <= INIT_OPX;
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else -- multiplication
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else -- multiplication
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start <= '1';
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start <= '1';
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state <= PROCESSING;
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state <= PROCESSING;
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| Line 183... |
Line 183... |
end if;
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end if;
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end if;
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end if;
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end process multiplier_core;
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end process multiplier_core;
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-- MUL: do another addition --
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-- MUL: do another addition --
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mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opy_is_signed, opx)
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mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx)
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begin
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begin
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if (mul_product(0) = '1') then
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if (mul_product(0) = '1') then
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if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB
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if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB
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mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opy'left) and opx_is_signed) & opx));
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mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opy'left) and opx_is_signed) & opx));
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else
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else
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