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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Co-Processor: MULDIV unit (RISC-V "M" Extension)>> #
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-- # << NEORV32 - CPU Co-Processor: Integer Multiplier/Divider Unit (RISC-V "M" Extension)>> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
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-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
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-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency #
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-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency #
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-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency #
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-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency #
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-- # Multiplications can be mapped to DSP block when FAST_MUL_EN = true. #
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-- # Multiplications can be mapped to DSP block when FAST_MUL_EN = true. #
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
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signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
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signal cp_op_ff : std_ulogic_vector(2 downto 0); -- operation that was executed
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signal cp_op_ff : std_ulogic_vector(2 downto 0); -- operation that was executed
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signal start : std_ulogic;
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signal start : std_ulogic;
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signal operation : std_ulogic;
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signal operation : std_ulogic;
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signal opx, opy : std_ulogic_vector(data_width_c-1 downto 0); -- input operands
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signal rs1, opx, opy : std_ulogic_vector(data_width_c-1 downto 0); -- input operands
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signal opx_is_signed : std_ulogic;
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signal opx_is_signed : std_ulogic;
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signal opy_is_signed : std_ulogic;
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signal opy_is_signed : std_ulogic;
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signal opy_is_zero : std_ulogic;
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signal opy_is_zero : std_ulogic;
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signal div_res_corr : std_ulogic;
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signal div_res_corr : std_ulogic;
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signal valid : std_ulogic;
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signal valid : std_ulogic;
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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state <= IDLE;
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state <= IDLE;
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opx <= (others => '0');
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opx <= (others => '0');
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opy <= (others => '0');
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opy <= (others => '0');
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rs1 <= (others => '0');
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cnt <= (others => '0');
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cnt <= (others => '0');
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start <= '0';
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start <= '0';
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valid <= '0';
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valid <= '0';
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div_res_corr <= '0';
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div_res_corr <= '0';
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opy_is_zero <= '0';
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opy_is_zero <= '0';
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cp_op_ff <= cp_op;
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cp_op_ff <= cp_op;
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-- FSM --
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-- FSM --
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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if (start_i = '1') then
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opx <= rs1_i;
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opx <= rs1_i;
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rs1 <= rs1_i;
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opy <= rs2_i;
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opy <= rs2_i;
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if (start_i = '1') then
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state <= DECODE;
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state <= DECODE;
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end if;
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end if;
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when DECODE =>
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when DECODE =>
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--
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--
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div_res <= div_sign_comp when (div_res_corr = '1') and (opy_is_zero = '0') else div_sign_comp_in;
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div_res <= div_sign_comp when (div_res_corr = '1') and (opy_is_zero = '0') else div_sign_comp_in;
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-- Data Output ----------------------------------------------------------------------------
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-- Data Output ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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operation_result: process(valid, cp_op_ff, mul_product, div_res, quotient, opy_is_zero, rs1_i, remainder)
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operation_result: process(valid, cp_op_ff, mul_product, div_res, quotient, opy_is_zero, rs1, remainder)
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begin
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begin
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if (valid = '1') then
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if (valid = '1') then
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case cp_op_ff is
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case cp_op_ff is
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when cp_op_mul_c =>
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when cp_op_mul_c =>
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res_o <= mul_product(31 downto 00);
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res_o <= mul_product(31 downto 00);
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res_o <= quotient;
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res_o <= quotient;
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when cp_op_rem_c =>
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when cp_op_rem_c =>
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if (opy_is_zero = '0') then
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if (opy_is_zero = '0') then
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res_o <= div_res;
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res_o <= div_res;
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else
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else
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res_o <= rs1_i;
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res_o <= rs1;
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end if;
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end if;
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when others => -- cp_op_remu_c
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when others => -- cp_op_remu_c
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res_o <= remainder;
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res_o <= remainder;
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end case;
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end case;
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else
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else
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