URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_decompressor.vhd] - Diff between revs 6 and 36
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 6 |
Rev 36 |
| Line 114... |
Line 114... |
when "00" => -- C0: Register-Based Loads and Stores
|
when "00" => -- C0: Register-Based Loads and Stores
|
case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is
|
case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is
|
|
|
when "000" => -- Illegal_instruction, C.ADDI4SPN
|
when "000" => -- Illegal_instruction, C.ADDI4SPN
|
-- ----------------------------------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------------------------------------
|
if (ci_instr16_i(12 downto 2) = "00000000000") then -- "official" illegal instruction
|
if (ci_instr16_i(12 downto 2) = "00000000000") then -- "official illegal instruction"
|
ci_illegal_o <= '1';
|
ci_illegal_o <= '1';
|
|
else
|
else -- C.ADDI4SPN
|
-- C.ADDI4SPN
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c);
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c);
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
|
ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => '0'); -- zero extend
|
ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => '0'); -- zero extend
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.