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-- register file --
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-- register file --
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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signal reg_file : reg_file_t;
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signal reg_file : reg_file_t;
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signal reg_file_emb : reg_file_emb_t;
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signal reg_file_emb : reg_file_emb_t;
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-- access --
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signal rf_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rf_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rd_is_x0 : std_ulogic; -- writing to x0?
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signal rd_zero : std_ulogic; -- writing to x0?
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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begin
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begin
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-- Data Input Mux -------------------------------------------------------------------------
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-- Data Input Mux -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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input_mux: process(rd_is_x0, ctrl_i, alu_i, mem_i, csr_i, pc2_i)
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input_mux: process(rd_zero, ctrl_i, alu_i, mem_i, csr_i, pc2_i)
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begin
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begin
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if (rd_is_x0 = '1') then -- write zero if accessing x0 to "emulate" it is hardwired to zero
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if (rd_zero = '1') then -- write zero if accessing x0 to "emulate" it is hardwired to zero
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rf_wdata <= (others => '0'); -- TODO: FIXME! but how???
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rf_wdata <= (others => '0'); -- TODO: FIXME! but how???
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else
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else
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case ctrl_i(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) is
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case ctrl_i(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) is
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when rf_mux_alu_c => rf_wdata <= alu_i; -- ALU result
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when rf_mux_alu_c => rf_wdata <= alu_i; -- ALU result
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when rf_mux_mem_c => rf_wdata <= mem_i; -- memory read data
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when rf_mux_mem_c => rf_wdata <= mem_i; -- memory read data
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when others => rf_wdata <= alu_i;
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when others => rf_wdata <= alu_i;
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end case;
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end case;
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end if;
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end if;
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end process input_mux;
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end process input_mux;
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-- writing to x0? --
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rd_zero <= '1' when (ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) = "00000") else '0';
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-- Register File Access -------------------------------------------------------------------
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-- Register File Access -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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reg_file_rv32i: -- normal register file with 32 registers
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reg_file_rv32i: -- normal register file with 32 registers
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if (CPU_EXTENSION_RISCV_E = false) generate
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if (CPU_EXTENSION_RISCV_E = false) generate
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end if;
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end if;
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rs1_o <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs1_o <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs2_o <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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rs2_o <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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end if;
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end if;
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end process rf_access;
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end process rf_access;
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-- writing to x0? --
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rd_is_x0 <= not or_reduce_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c));
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end generate;
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end generate;
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reg_file_rv32e: -- embedded register file with 16 registers
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reg_file_rv32e: -- embedded register file with 16 registers
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if (CPU_EXTENSION_RISCV_E = true) generate
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if (CPU_EXTENSION_RISCV_E = true) generate
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rf_access: process(clk_i)
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rf_access: process(clk_i)
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end if;
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end if;
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rs1_o <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs1_o <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs2_o <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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rs2_o <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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end if;
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end if;
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end process rf_access;
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end process rf_access;
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-- writing to x0? --
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rd_is_x0 <= not or_reduce_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
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end generate;
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end generate;
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-- access addresses --
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-- access addresses --
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opa_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_wb_en_c) = '1') else
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opa_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_wb_en_c) = '1') else
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ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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