| Line 61... |
Line 61... |
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- data output --
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-- data output --
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
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cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status
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);
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);
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end neorv32_cpu_regfile;
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end neorv32_cpu_regfile;
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architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
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architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
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| Line 79... |
Line 80... |
signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rf_we : std_ulogic;
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signal rf_we : std_ulogic;
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0);
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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begin
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begin
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-- Data Input Mux -------------------------------------------------------------------------
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-- Data Input Mux -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 97... |
Line 103... |
if rising_edge(clk_i) then -- sync read and write
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if rising_edge(clk_i) then -- sync read and write
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (rf_we = '1') then
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if (rf_we = '1') then
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_write_data;
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_write_data;
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end if;
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end if;
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rs1_o <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs2_o <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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else -- embedded register file with 16 entries
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else -- embedded register file with 16 entries
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if (rf_we = '1') then
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if (rf_we = '1') then
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_write_data;
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_write_data;
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end if;
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end if;
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rs1_o <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs2_o <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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end if;
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end if;
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end if;
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end if;
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end process rf_access;
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end process rf_access;
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-- check if we are writing to x0 --
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-- check if we are writing to x0 --
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| Line 123... |
Line 129... |
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-- access addresses --
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-- access addresses --
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opa_addr <= dst_addr when (rf_we = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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opa_addr <= dst_addr when (rf_we = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
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opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
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-- data output --
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rs1_o <= rs1;
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rs2_o <= rs2;
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-- Comparator Unit (for conditional branches) ---------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_opx <= (rs1(rs1'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1;
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cmp_opy <= (rs2(rs2'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2;
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cmp_o(cmp_equal_c) <= '1' when (rs1 = rs2) else '0';
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cmp_o(cmp_less_c) <= '1' when (signed(cmp_opx) < signed(cmp_opy)) else '0';
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end neorv32_cpu_regfile_rtl;
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end neorv32_cpu_regfile_rtl;
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No newline at end of file
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No newline at end of file
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