| Line 2... |
Line 2... |
-- # << NEORV32 - CPU General Purpose Data Register File >> #
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-- # << NEORV32 - CPU General Purpose Data Register File >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # General purpose data register file. 32 entries (= 1024 bit) for normal mode (RV32I), #
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-- # General purpose data register file. 32 entries (= 1024 bit) for normal mode (RV32I), #
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-- # 16 entries (= 512 bit) for embedded mode (RV32E) when RISC-V "E" extension is enabled. #
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-- # 16 entries (= 512 bit) for embedded mode (RV32E) when RISC-V "E" extension is enabled. #
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-- # #
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-- # #
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-- # Register zero (r0/x0) is a "normal" physical reg that has to be initialized to zero by the #
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-- # Register zero (r0/x0) is a "normal" physical register that has to be initialized to zero by #
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-- # CPU control system. For normal operations register zero cannot be written. #
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-- # the early boot code. Register zero is always set to zero when written. #
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-- # #
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-- # #
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-- # The register file uses synchronous read accesses and a *single* (multiplexed) address port #
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-- # The register file uses synchronous read accesses and a *single* (multiplexed) address port #
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-- # for writing and reading rs1 and a single read-only port for rs2. Therefore, the whole #
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-- # for writing and reading rd/rs1 and a single read-only port for rs2. Therefore, the whole #
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-- # register file can be mapped to a single true dual-port block RAM. #
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-- # register file can be mapped to a single true-dual-port block RAM. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 60... |
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-- data input --
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-- data input --
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- data output --
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-- data output --
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
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cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status
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);
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);
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end neorv32_cpu_regfile;
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end neorv32_cpu_regfile;
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|
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architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
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architecture neorv32_cpu_regfile_rtl of neorv32_cpu_regfile is
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| Line 79... |
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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|
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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|
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begin
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begin
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|
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-- Data Input Mux -------------------------------------------------------------------------
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-- Data Input Mux -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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input_mux: process(rd_is_r0, ctrl_i, alu_i, mem_i)
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input_mux: process(rd_is_r0, ctrl_i, alu_i, mem_i)
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| Line 135... |
Line 130... |
-- data output --
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-- data output --
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rs1_o <= rs1;
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rs1_o <= rs1;
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rs2_o <= rs2;
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rs2_o <= rs2;
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|
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-- Comparator Unit (for conditional branches) ---------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_opx <= (rs1(rs1'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1;
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cmp_opy <= (rs2(rs2'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2;
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|
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cmp_o(cmp_equal_c) <= '1' when (rs1 = rs2) else '0';
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cmp_o(cmp_less_c) <= '1' when (signed(cmp_opx) < signed(cmp_opy)) else '0';
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end neorv32_cpu_regfile_rtl;
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end neorv32_cpu_regfile_rtl;
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