| Line 1... |
Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> #
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-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # 32-bit parallel input & output unit. Any pin change (HI->LO or LO->HI) of an enabled input #
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-- # 64-bit general purpose parallel input & output port unit. #
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-- # pin (via irq_en register) triggers an IRQ. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 51... |
Line 50... |
wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- parallel io --
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-- parallel io --
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gpio_o : out std_ulogic_vector(31 downto 0);
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gpio_o : out std_ulogic_vector(63 downto 0);
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gpio_i : in std_ulogic_vector(31 downto 0);
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gpio_i : in std_ulogic_vector(63 downto 0)
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-- interrupt --
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irq_o : out std_ulogic
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);
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);
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end neorv32_gpio;
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end neorv32_gpio;
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|
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architecture neorv32_gpio_rtl of neorv32_gpio is
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architecture neorv32_gpio_rtl of neorv32_gpio is
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| Line 69... |
Line 66... |
-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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-- accessible regs --
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-- accessible regs --
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signal din : std_ulogic_vector(31 downto 0); -- r/-
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signal din_lo, din_hi : std_ulogic_vector(31 downto 0); -- r/-
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signal dout : std_ulogic_vector(31 downto 0); -- r/w
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signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0); -- r/w
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signal irq_en : std_ulogic_vector(31 downto 0); -- -/w, uses the same address as data_in
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-- misc --
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signal in_buf : std_ulogic_vector(31 downto 0);
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|
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begin
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begin
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|
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 89... |
Line 82... |
-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rw_access: process(clk_i)
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rw_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- bus handshake --
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= acc_en and (rden_i or wren_i);
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|
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-- write access --
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-- write access --
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if ((acc_en and wren_i) = '1') then
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if ((acc_en and wren_i) = '1') then
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if (addr = gpio_in_addr_c) then
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if (addr = gpio_out_lo_addr_c) then
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irq_en <= data_i; -- pin change IRQ enable
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dout_lo <= data_i;
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else -- gpio_out_addr_c
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end if;
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dout <= data_i; -- data output port
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if (addr = gpio_out_hi_addr_c) then
|
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dout_hi <= data_i;
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end if;
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end if;
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end if;
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end if;
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|
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-- input buffer --
|
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din_lo <= gpio_i(31 downto 00);
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din_hi <= gpio_i(63 downto 32);
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|
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if ((acc_en and rden_i) = '1') then
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if ((acc_en and rden_i) = '1') then
|
if (addr = gpio_in_addr_c) then
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case addr is
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data_o <= din; -- data input port
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when gpio_in_lo_addr_c => data_o <= din_lo;
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else -- gpio_out_addr_c
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when gpio_in_hi_addr_c => data_o <= din_hi;
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data_o <= dout; -- data output port
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when gpio_out_lo_addr_c => data_o <= dout_lo;
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end if;
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when gpio_out_hi_addr_c => data_o <= dout_hi;
|
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when others => data_o <= (others => '0');
|
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end case;
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end if;
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end if;
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|
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end if;
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end if;
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end process rw_access;
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end process rw_access;
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|
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-- output --
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-- output --
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gpio_o <= dout;
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gpio_o <= dout_hi & dout_lo;
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|
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|
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-- IRQ Detector ------------------------------------------------------------
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|
-- -----------------------------------------------------------------------------
|
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irq_detector: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
-- input synchronizer --
|
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in_buf <= gpio_i;
|
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din <= in_buf;
|
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-- IRQ --
|
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irq_o <= or_reduce_f((in_buf xor din) and irq_en); -- any enabled pin transition triggers an interrupt
|
|
end if;
|
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end process irq_detector;
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|
|
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end neorv32_gpio_rtl;
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end neorv32_gpio_rtl;
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No newline at end of file
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No newline at end of file
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