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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> #
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-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # 64-bit general purpose parallel input & output port unit. #
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-- # 64-bit general purpose parallel input & output port unit. Input/outputs are split into two #
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-- # 32-bit memory-mapped registers each. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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-- parallel io --
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-- parallel io --
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gpio_o : out std_ulogic_vector(63 downto 0);
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gpio_o : out std_ulogic_vector(63 downto 0);
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gpio_i : in std_ulogic_vector(63 downto 0)
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gpio_i : in std_ulogic_vector(63 downto 0)
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);
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);
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end neorv32_gpio;
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end neorv32_gpio;
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- word write enable
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signal wren : std_ulogic; -- word write enable
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signal rden : std_ulogic; -- read enable
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signal rden : std_ulogic; -- read enable
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-- accessible regs --
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-- accessible regs --
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signal din_lo, din_hi : std_ulogic_vector(31 downto 0); -- r/-
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signal din_hi, din_lo : std_ulogic_vector(31 downto 0); -- r/-: parallel input hi/lo
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signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0); -- r/w
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signal dout_hi, dout_lo : std_ulogic_vector(31 downto 0); -- r/w: parallel output hi/lo
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begin
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begin
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rw_access: process(clk_i)
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rw_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- bus handshake --
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-- bus handshake --
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ack_o <= wren or rden;
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ack_o <= (wren and addr(3)) or rden;
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err_o <= wren and (not addr(3)); -- INPUT registers are read only!
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-- write access --
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-- write access --
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if (wren = '1') then
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if (wren = '1') then
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if (addr = gpio_out_lo_addr_c) then
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if (addr = gpio_out_lo_addr_c) then
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dout_lo <= data_i;
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dout_lo <= data_i;
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if (addr = gpio_out_hi_addr_c) then
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if (addr = gpio_out_hi_addr_c) then
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dout_hi <= data_i;
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dout_hi <= data_i;
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end if;
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end if;
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end if;
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end if;
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-- input buffer --
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-- input buffer (prevent metastability) --
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din_lo <= gpio_i(31 downto 00);
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din_lo <= gpio_i(31 downto 00);
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din_hi <= gpio_i(63 downto 32);
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din_hi <= gpio_i(63 downto 32);
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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