| Line 4... |
Line 4... |
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2). #
|
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2). #
|
-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1). #
|
-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1). #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # permitted provided that the following conditions are met: #
|
-- # permitted provided that the following conditions are met: #
|
-- # #
|
-- # #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
| Line 59... |
Line 59... |
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
host_we_i : in std_ulogic; -- write enable
|
host_we_i : in std_ulogic; -- write enable
|
host_re_i : in std_ulogic; -- read enable
|
host_re_i : in std_ulogic; -- read enable
|
host_cancel_i : in std_ulogic; -- cancel current bus transaction
|
host_cancel_i : in std_ulogic; -- cancel current bus transaction
|
host_lock_i : in std_ulogic; -- locked/exclusive access
|
|
host_ack_o : out std_ulogic; -- bus transfer acknowledge
|
host_ack_o : out std_ulogic; -- bus transfer acknowledge
|
host_err_o : out std_ulogic; -- bus transfer error
|
host_err_o : out std_ulogic; -- bus transfer error
|
-- peripheral bus interface --
|
-- peripheral bus interface --
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_we_o : out std_ulogic; -- write enable
|
bus_we_o : out std_ulogic; -- write enable
|
bus_re_o : out std_ulogic; -- read enable
|
bus_re_o : out std_ulogic; -- read enable
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_lock_o : out std_ulogic; -- locked/exclusive access
|
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_err_i : in std_ulogic -- bus transfer error
|
bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end neorv32_icache;
|
end neorv32_icache;
|
|
|
| Line 186... |
Line 184... |
end process ctrl_engine_fsm_sync;
|
end process ctrl_engine_fsm_sync;
|
|
|
|
|
-- Control Engine FSM Comb ----------------------------------------------------------------
|
-- Control Engine FSM Comb ----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ctrl_engine_fsm_comb: process(ctrl, cache, clear_i, host_addr_i, host_lock_i, host_re_i, host_cancel_i, bus_rdata_i, bus_ack_i, bus_err_i)
|
ctrl_engine_fsm_comb: process(ctrl, cache, clear_i, host_addr_i, host_re_i, host_cancel_i, bus_rdata_i, bus_ack_i, bus_err_i)
|
begin
|
begin
|
-- control defaults --
|
-- control defaults --
|
ctrl.state_nxt <= ctrl.state;
|
ctrl.state_nxt <= ctrl.state;
|
ctrl.addr_reg_nxt <= ctrl.addr_reg;
|
ctrl.addr_reg_nxt <= ctrl.addr_reg;
|
ctrl.re_buf_nxt <= (ctrl.re_buf or host_re_i) and (not host_cancel_i);
|
ctrl.re_buf_nxt <= (ctrl.re_buf or host_re_i) and (not host_cancel_i);
|
| Line 217... |
Line 215... |
bus_wdata_o <= (others => '0'); -- cache is read-only
|
bus_wdata_o <= (others => '0'); -- cache is read-only
|
bus_ben_o <= (others => '0'); -- cache is read-only
|
bus_ben_o <= (others => '0'); -- cache is read-only
|
bus_we_o <= '0'; -- cache is read-only
|
bus_we_o <= '0'; -- cache is read-only
|
bus_re_o <= '0';
|
bus_re_o <= '0';
|
bus_cancel_o <= '0';
|
bus_cancel_o <= '0';
|
bus_lock_o <= host_lock_i;
|
|
|
|
-- fsm --
|
-- fsm --
|
case ctrl.state is
|
case ctrl.state is
|
|
|
when S_IDLE => -- wait for host access request or cache control operation
|
when S_IDLE => -- wait for host access request or cache control operation
|
