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Line 48... |
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entity neorv32_mtime is
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entity neorv32_mtime is
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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Line 73... |
signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- module access enable
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signal wren : std_ulogic; -- module access enable
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-- accessible regs --
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-- accessible regs --
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signal mtime_we : std_ulogic;
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signal mtimecmp : std_ulogic_vector(63 downto 0);
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signal mtimecmp : std_ulogic_vector(63 downto 0);
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signal mtime_lo : std_ulogic_vector(32 downto 0);
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signal mtime_lo : std_ulogic_vector(32 downto 0);
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signal mtime_lo_msb_ff : std_ulogic;
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signal mtime_lo_msb_ff : std_ulogic;
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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Line 95... |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i;
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wren <= acc_en and wren_i;
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-- System Time Update ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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system_time: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (rstn_i = '0') then
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mtime_lo <= (others => '0');
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mtime_hi <= (others => '0');
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else
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-- mtime low --
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mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
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-- mtime high --
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if ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
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end if;
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end if;
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end if;
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end process system_time;
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-- Write Access ---------------------------------------------------------------------------
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-- Write Access ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wr_access: process(clk_i)
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wr_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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Line 138... |
if (ben_i(i) = '1') then
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if (ben_i(i) = '1') then
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mtimecmp(32+7+i*8 downto 32+0+i*8) <= data_i(7+i*8 downto 0+i*8);
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mtimecmp(32+7+i*8 downto 32+0+i*8) <= data_i(7+i*8 downto 0+i*8);
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end if;
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end if;
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end loop; -- byte enable
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end loop; -- byte enable
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end if;
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end if;
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-- any access to mtime at all? --
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mtime_we <= '0';
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if (wren = '1') and ((addr = mtime_time_lo_addr_c) or (addr = mtime_time_hi_addr_c)) then
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mtime_we <= '1';
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end if;
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-- mtime low --
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mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
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if (wren = '1') and (addr = mtime_time_lo_addr_c) then
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mtime_lo(mtime_lo'left) <= '0'; -- clear overflow bit on every access
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for i in 0 to 3 loop
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if (ben_i(i) = '1') then
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mtime_lo(00+7+i*8 downto 00+0+i*8) <= data_i(7+i*8 downto 0+i*8);
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end if;
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end loop; -- byte enable
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else -- incrment
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mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
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end if;
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-- mtime high --
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if (wren = '1') and (addr = mtime_time_hi_addr_c) then
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for i in 0 to 3 loop
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if (ben_i(i) = '1') then
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mtime_hi(00+7+i*8 downto 00+0+i*8) <= data_i(7+i*8 downto 0+i*8);
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end if;
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end loop; -- byte enable
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elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
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end if;
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end if;
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end if;
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end process wr_access;
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end process wr_access;
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-- Read Access ----------------------------------------------------------------------------
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-- Read Access ----------------------------------------------------------------------------
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Line 183... |
-- Interrupt Logic ------------------------------------------------------------------------
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-- Interrupt Logic ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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irq_ctrl: process(clk_i)
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irq_ctrl: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (rstn_i = '0') then
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irq_flag_ff <= '0';
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irq_flag <= '0';
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else
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irq_flag_ff <= irq_flag;
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irq_flag_ff <= irq_flag;
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if (irq_flag = '0') or (mtime_we = '1') then -- idle or mtime manual write
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if (irq_flag = '0') then -- idle
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irq_flag <= '0';
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irq_flag <= '0';
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if (cmp_match_ff = '1') then
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if (cmp_match_ff = '1') then
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irq_flag <= '1';
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irq_flag <= '1';
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end if;
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end if;
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elsif (wren = '1') and (addr = mtime_cmp_hi_addr_c) then -- ACK
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elsif (wren = '1') and (addr = mtime_cmp_hi_addr_c) then -- ACK
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irq_flag <= '0';
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irq_flag <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process irq_ctrl;
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end process irq_ctrl;
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-- irq output to CPU --
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-- irq output to CPU --
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irq_o <= irq_flag and (not irq_flag_ff); -- rising edge detector
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irq_o <= irq_flag and (not irq_flag_ff); -- rising edge detector
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