| Line 11... |
Line 11... |
-- # configurable via the control register's clock prescaler bits (ctrl_clksel*_c) and the period #
|
-- # configurable via the control register's clock prescaler bits (ctrl_clksel*_c) and the period #
|
-- # length configuration bits (ctrl_t_tot_*_c). "high-times" for sending a ZERO or a ONE bit are #
|
-- # length configuration bits (ctrl_t_tot_*_c). "high-times" for sending a ZERO or a ONE bit are #
|
-- # configured using the ctrl_t_0h_*_c and ctrl_t_1h_*_c bits, respectively. 32-bit transfers #
|
-- # configured using the ctrl_t_0h_*_c and ctrl_t_1h_*_c bits, respectively. 32-bit transfers #
|
-- # (for RGBW modules) and 24-bit transfers (for RGB modules) are supported via ctrl_mode__c. #
|
-- # (for RGBW modules) and 24-bit transfers (for RGB modules) are supported via ctrl_mode__c. #
|
-- # #
|
-- # #
|
-- # The device features a TX buffer (FIFO) with <FIFO_DEPTH> entries. An IRQ is triggered if the #
|
-- # The device features a TX buffer (FIFO) with <FIFO_DEPTH> entries with configurable interrupt. #
|
-- # FIFO falls below "half-full" fill level. #
|
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
| Line 119... |
Line 118... |
constant ctrl_t_1h_1_c : natural := 21; -- r/w: pulse-clock ticks per ONE high-time bit 1
|
constant ctrl_t_1h_1_c : natural := 21; -- r/w: pulse-clock ticks per ONE high-time bit 1
|
constant ctrl_t_1h_2_c : natural := 22; -- r/w: pulse-clock ticks per ONE high-time bit 2
|
constant ctrl_t_1h_2_c : natural := 22; -- r/w: pulse-clock ticks per ONE high-time bit 2
|
constant ctrl_t_1h_3_c : natural := 23; -- r/w: pulse-clock ticks per ONE high-time bit 3
|
constant ctrl_t_1h_3_c : natural := 23; -- r/w: pulse-clock ticks per ONE high-time bit 3
|
constant ctrl_t_1h_4_c : natural := 24; -- r/w: pulse-clock ticks per ONE high-time bit 4
|
constant ctrl_t_1h_4_c : natural := 24; -- r/w: pulse-clock ticks per ONE high-time bit 4
|
--
|
--
|
|
constant ctrl_irq_conf_c : natural := 27; -- r/w: interrupt config: 1=IRQ when buffer is empty, 0=IRQ when buffer is half-empty
|
constant ctrl_tx_empty_c : natural := 28; -- r/-: TX FIFO is empty
|
constant ctrl_tx_empty_c : natural := 28; -- r/-: TX FIFO is empty
|
constant ctrl_tx_half_c : natural := 29; -- r/-: TX FIFO is at least half-full
|
constant ctrl_tx_half_c : natural := 29; -- r/-: TX FIFO is at least half-full
|
constant ctrl_tx_full_c : natural := 30; -- r/-: TX FIFO is full
|
constant ctrl_tx_full_c : natural := 30; -- r/-: TX FIFO is full
|
constant ctrl_tx_busy_c : natural := 31; -- r/-: serial TX engine busy when set
|
constant ctrl_tx_busy_c : natural := 31; -- r/-: serial TX engine busy when set
|
|
|
| Line 130... |
Line 130... |
type ctrl_t is record
|
type ctrl_t is record
|
enable : std_ulogic;
|
enable : std_ulogic;
|
mode : std_ulogic;
|
mode : std_ulogic;
|
strobe : std_ulogic;
|
strobe : std_ulogic;
|
clk_prsc : std_ulogic_vector(2 downto 0);
|
clk_prsc : std_ulogic_vector(2 downto 0);
|
|
irq_conf : std_ulogic;
|
-- pulse config --
|
-- pulse config --
|
t_total : std_ulogic_vector(4 downto 0);
|
t_total : std_ulogic_vector(4 downto 0);
|
t0_high : std_ulogic_vector(4 downto 0);
|
t0_high : std_ulogic_vector(4 downto 0);
|
t1_high : std_ulogic_vector(4 downto 0);
|
t1_high : std_ulogic_vector(4 downto 0);
|
end record;
|
end record;
|
| Line 142... |
Line 143... |
-- transmission buffer --
|
-- transmission buffer --
|
type tx_buffer_t is record
|
type tx_buffer_t is record
|
we : std_ulogic; -- write enable
|
we : std_ulogic; -- write enable
|
re : std_ulogic; -- read enable
|
re : std_ulogic; -- read enable
|
clear : std_ulogic; -- sync reset, high-active
|
clear : std_ulogic; -- sync reset, high-active
|
level : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0);
|
|
wdata : std_ulogic_vector(31+2 downto 0); -- write data (excluding mode)
|
wdata : std_ulogic_vector(31+2 downto 0); -- write data (excluding mode)
|
rdata : std_ulogic_vector(31+2 downto 0); -- read data (including mode)
|
rdata : std_ulogic_vector(31+2 downto 0); -- read data (including mode)
|
avail : std_ulogic; -- data available?
|
avail : std_ulogic; -- data available?
|
free : std_ulogic; -- free entry available?
|
free : std_ulogic; -- free entry available?
|
half : std_ulogic; -- half full
|
half : std_ulogic; -- half full
|
half_ff : std_ulogic;
|
|
end record;
|
end record;
|
signal tx_buffer : tx_buffer_t;
|
signal tx_buffer : tx_buffer_t;
|
|
|
-- serial transmission engine --
|
-- serial transmission engine --
|
type serial_state_t is (S_IDLE, S_INIT, S_GETBIT, S_PULSE, S_STROBE);
|
type serial_state_t is (S_IDLE, S_INIT, S_GETBIT, S_PULSE, S_STROBE);
|
| Line 202... |
Line 201... |
if (wren = '1') and (addr = neoled_ctrl_addr_c) then
|
if (wren = '1') and (addr = neoled_ctrl_addr_c) then
|
ctrl.enable <= data_i(ctrl_enable_c);
|
ctrl.enable <= data_i(ctrl_enable_c);
|
ctrl.mode <= data_i(ctrl_mode_c);
|
ctrl.mode <= data_i(ctrl_mode_c);
|
ctrl.strobe <= data_i(ctrl_strobe_c);
|
ctrl.strobe <= data_i(ctrl_strobe_c);
|
ctrl.clk_prsc <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
|
ctrl.clk_prsc <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
|
|
ctrl.irq_conf <= data_i(ctrl_irq_conf_c);
|
ctrl.t_total <= data_i(ctrl_t_tot_4_c downto ctrl_t_tot_0_c);
|
ctrl.t_total <= data_i(ctrl_t_tot_4_c downto ctrl_t_tot_0_c);
|
ctrl.t0_high <= data_i(ctrl_t_0h_4_c downto ctrl_t_0h_0_c);
|
ctrl.t0_high <= data_i(ctrl_t_0h_4_c downto ctrl_t_0h_0_c);
|
ctrl.t1_high <= data_i(ctrl_t_1h_4_c downto ctrl_t_1h_0_c);
|
ctrl.t1_high <= data_i(ctrl_t_1h_4_c downto ctrl_t_1h_0_c);
|
end if;
|
end if;
|
|
|
| Line 214... |
Line 214... |
if (rden = '1') then -- and (addr = neoled_ctrl_addr_c) then
|
if (rden = '1') then -- and (addr = neoled_ctrl_addr_c) then
|
data_o(ctrl_enable_c) <= ctrl.enable;
|
data_o(ctrl_enable_c) <= ctrl.enable;
|
data_o(ctrl_mode_c) <= ctrl.mode;
|
data_o(ctrl_mode_c) <= ctrl.mode;
|
data_o(ctrl_strobe_c) <= ctrl.strobe;
|
data_o(ctrl_strobe_c) <= ctrl.strobe;
|
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_prsc;
|
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl.clk_prsc;
|
|
data_o(ctrl_irq_conf_c) <= ctrl.irq_conf or bool_to_ulogic_f(boolean(FIFO_DEPTH = 1)); -- tie to one if FIFO_DEPTH is 1
|
data_o(ctrl_bufs_3_c downto ctrl_bufs_0_c) <= std_ulogic_vector(to_unsigned(index_size_f(FIFO_DEPTH), 4));
|
data_o(ctrl_bufs_3_c downto ctrl_bufs_0_c) <= std_ulogic_vector(to_unsigned(index_size_f(FIFO_DEPTH), 4));
|
data_o(ctrl_t_tot_4_c downto ctrl_t_tot_0_c) <= ctrl.t_total;
|
data_o(ctrl_t_tot_4_c downto ctrl_t_tot_0_c) <= ctrl.t_total;
|
data_o(ctrl_t_0h_4_c downto ctrl_t_0h_0_c) <= ctrl.t0_high;
|
data_o(ctrl_t_0h_4_c downto ctrl_t_0h_0_c) <= ctrl.t0_high;
|
data_o(ctrl_t_1h_4_c downto ctrl_t_1h_0_c) <= ctrl.t1_high;
|
data_o(ctrl_t_1h_4_c downto ctrl_t_1h_0_c) <= ctrl.t1_high;
|
--
|
--
|
| Line 241... |
Line 242... |
-- IRQ Generator --------------------------------------------------------------------------
|
-- IRQ Generator --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
irq_generator: process(clk_i)
|
irq_generator: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
tx_buffer.half_ff <= tx_buffer.half;
|
if (ctrl.enable = '0') then
|
irq_o <= ctrl.enable and tx_buffer.half and (not tx_buffer.half_ff); -- FIFO _becomes_ half-full
|
irq_o <= '0'; -- no interrupt if unit is disabled
|
|
else
|
|
if (FIFO_DEPTH = 1) then
|
|
irq_o <= tx_buffer.free; -- fire IRQ if FIFO is empty
|
|
else
|
|
if (ctrl.irq_conf = '0') then -- fire IRQ if FIFO is less than half-full
|
|
irq_o <= not tx_buffer.half;
|
|
else -- fire IRQ if FIFO is empty
|
|
irq_o <= tx_buffer.free;
|
|
end if;
|
|
end if;
|
|
end if;
|
end if;
|
end if;
|
end process irq_generator;
|
end process irq_generator;
|
|
|
|
|
-- TX Buffer (FIFO) -----------------------------------------------------------------------
|
-- TX Buffer (FIFO) -----------------------------------------------------------------------
|
| Line 261... |
Line 273... |
port map (
|
port map (
|
-- control --
|
-- control --
|
clk_i => clk_i, -- clock, rising edge
|
clk_i => clk_i, -- clock, rising edge
|
rstn_i => '1', -- async reset, low-active
|
rstn_i => '1', -- async reset, low-active
|
clear_i => tx_buffer.clear, -- sync reset, high-active
|
clear_i => tx_buffer.clear, -- sync reset, high-active
|
level_o => tx_buffer.level, -- fill level
|
level_o => open, -- fill level
|
|
half_o => tx_buffer.half, -- FIFO is at least half full
|
-- write port --
|
-- write port --
|
wdata_i => tx_buffer.wdata, -- write data
|
wdata_i => tx_buffer.wdata, -- write data
|
we_i => tx_buffer.we, -- write enable
|
we_i => tx_buffer.we, -- write enable
|
free_o => tx_buffer.free, -- at least one entry is free when set
|
free_o => tx_buffer.free, -- at least one entry is free when set
|
-- read port --
|
-- read port --
|
re_i => tx_buffer.re, -- read enable
|
re_i => tx_buffer.re, -- read enable
|
rdata_o => tx_buffer.rdata, -- read data
|
rdata_o => tx_buffer.rdata, -- read data
|
avail_o => tx_buffer.avail -- data available when set
|
avail_o => tx_buffer.avail -- data available when set
|
);
|
);
|
|
|
-- FIFO half-full? --
|
-- try to get new TX data --
|
tx_buffer.half <= '1' when (unsigned(tx_buffer.level) >= to_unsigned(cond_sel_natural_f(boolean(FIFO_DEPTH > 1), FIFO_DEPTH/2, 1), tx_buffer.level'length)) else '0';
|
tx_buffer.re <= '1' when (serial.state = S_IDLE) else '0';
|
|
|
|
|
-- Serial TX Engine -----------------------------------------------------------------------
|
-- Serial TX Engine -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
serial_engine: process(clk_i)
|
serial_engine: process(clk_i)
|
| Line 320... |
Line 333... |
when S_GETBIT => -- get next TX bit
|
when S_GETBIT => -- get next TX bit
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
serial.sreg <= serial.sreg(serial.sreg'left-1 downto 0) & '0'; -- shift left by one position (MSB-first)
|
serial.sreg <= serial.sreg(serial.sreg'left-1 downto 0) & '0'; -- shift left by one position (MSB-first)
|
serial.bit_cnt <= std_ulogic_vector(unsigned(serial.bit_cnt) - 1);
|
serial.bit_cnt <= std_ulogic_vector(unsigned(serial.bit_cnt) - 1);
|
serial.pulse_cnt <= (others => '0');
|
serial.pulse_cnt <= (others => '0');
|
if (serial.bit_cnt = "000000") then -- all done?
|
|
serial.state <= S_IDLE;
|
|
else -- check current data MSB
|
|
if (serial.next_bit = '0') then -- send zero-bit
|
if (serial.next_bit = '0') then -- send zero-bit
|
serial.t_high <= ctrl.t0_high;
|
serial.t_high <= ctrl.t0_high;
|
else -- send one-bit
|
else -- send one-bit
|
serial.t_high <= ctrl.t1_high;
|
serial.t_high <= ctrl.t1_high;
|
end if;
|
end if;
|
serial.state <= S_PULSE; -- transmit single pulse
|
if (serial.bit_cnt = "000000") then -- all done?
|
|
serial.tx_out <= '0';
|
|
serial.state <= S_IDLE;
|
|
else -- send current data MSB
|
serial.tx_out <= '1';
|
serial.tx_out <= '1';
|
|
serial.state <= S_PULSE; -- transmit single pulse
|
end if;
|
end if;
|
|
|
when S_PULSE => -- send pulse with specific duty cycle
|
when S_PULSE => -- send pulse with specific duty cycle
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- total pulse length = ctrl.t_total
|
-- total pulse length = ctrl.t_total
|
| Line 379... |
Line 393... |
end process serial_engine;
|
end process serial_engine;
|
|
|
-- SREG's TX data: bit 23 for RGB mode (24-bit), bit 31 for RGBW mode (32-bit) --
|
-- SREG's TX data: bit 23 for RGB mode (24-bit), bit 31 for RGBW mode (32-bit) --
|
serial.next_bit <= serial.sreg(23) when (serial.mode = '0') else serial.sreg(31);
|
serial.next_bit <= serial.sreg(23) when (serial.mode = '0') else serial.sreg(31);
|
|
|
-- get new TX data --
|
|
tx_buffer.re <= '1' when (serial.state = S_IDLE) and (tx_buffer.avail = '1') else '0';
|
|
|
|
-- TX engine status --
|
-- TX engine status --
|
serial.busy <= '0' when (serial.state = S_IDLE) or (ctrl.enable = '0') else '1';
|
serial.busy <= '0' when (serial.state = S_IDLE) else '1';
|
|
|
|
|
end neorv32_neoled_rtl;
|
end neorv32_neoled_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
