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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030000"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030500"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function index_size_f(input : natural) return natural;
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function index_size_f(input : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function and_all_f( a : std_ulogic_vector) return std_ulogic;
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function and_all_f( a : std_ulogic_vector) return std_ulogic;
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function xor_all_f( a : std_ulogic_vector) return std_ulogic;
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function xor_all_f( a : std_ulogic_vector) return std_ulogic;
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
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function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
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function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
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-- Internal Types -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
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type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
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-- Processor-internal Address Space Layout ------------------------------------------------
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-- Processor-internal Address Space Layout ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Instruction Memory & Data Memory --
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-- Instruction Memory & Data Memory --
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-- => configured via top's generics
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-- => configured via top's generics
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constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
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constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
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constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
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constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
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--
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--
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constant interrupt_width_c : natural := 7; -- length of this list in bits
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constant interrupt_width_c : natural := 7; -- length of this list in bits
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-- CPU Privilege Modes --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant m_priv_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
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constant u_priv_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
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-- Clock Generator -------------------------------------------------------------------------
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-- Clock Generator -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant clk_div2_c : natural := 0;
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constant clk_div2_c : natural := 0;
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constant clk_div4_c : natural := 1;
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constant clk_div4_c : natural := 1;
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constant clk_div8_c : natural := 2;
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constant clk_div8_c : natural := 2;
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USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
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USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
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PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Memory configuration: Instruction memory --
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
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PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Bus Interface --
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-- Bus Interface --
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical memory protection (PMP) --
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PMP_USE : boolean := false; -- implement physical memory protection?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
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PMP_GRANULARITY : natural := 0 -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(3 downto 0);
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firq_i : in std_ulogic_vector(3 downto 0);
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- physical memory protection --
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pmp_addr_o : out pmp_addr_if_t; -- addresses
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pmp_maddr_i : in pmp_addr_if_t; -- masked addresses
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pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
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priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- bus access exceptions --
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-- bus access exceptions --
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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-- Component: CPU Bus Interface -----------------------------------------------------------
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-- Component: CPU Bus Interface -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_bus
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component neorv32_cpu_bus
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
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-- Physical memory protection (PMP) --
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PMP_USE : boolean := false; -- implement physical memory protection?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
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PMP_GRANULARITY : natural := 0 -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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Line 693... |
--
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--
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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-- physical memory protection --
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pmp_addr_i : in pmp_addr_if_t; -- addresses
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pmp_maddr_o : out pmp_addr_if_t; -- masked addresses
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pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
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priv_mode_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- instruction bus --
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-- instruction bus --
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function or_all_f(a : std_ulogic_vector) return std_ulogic is
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function or_all_f(a : std_ulogic_vector) return std_ulogic is
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variable tmp_v : std_ulogic;
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variable tmp_v : std_ulogic;
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begin
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begin
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tmp_v := a(a'low);
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tmp_v := a(a'low);
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if (a'low < a'high) then -- not null range?
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for i in a'low+1 to a'high loop
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for i in a'low+1 to a'high loop
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tmp_v := tmp_v or a(i);
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tmp_v := tmp_v or a(i);
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end loop; -- i
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end loop; -- i
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end if;
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return tmp_v;
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return tmp_v;
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end function or_all_f;
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end function or_all_f;
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-- Function: AND all bits -----------------------------------------------------------------
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-- Function: AND all bits -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function and_all_f(a : std_ulogic_vector) return std_ulogic is
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function and_all_f(a : std_ulogic_vector) return std_ulogic is
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variable tmp_v : std_ulogic;
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variable tmp_v : std_ulogic;
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begin
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begin
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tmp_v := a(a'low);
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tmp_v := a(a'low);
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if (a'low < a'high) then -- not null range?
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for i in a'low+1 to a'high loop
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for i in a'low+1 to a'high loop
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tmp_v := tmp_v and a(i);
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tmp_v := tmp_v and a(i);
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end loop; -- i
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end loop; -- i
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end if;
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return tmp_v;
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return tmp_v;
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end function and_all_f;
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end function and_all_f;
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-- Function: XOR all bits -----------------------------------------------------------------
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-- Function: XOR all bits -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function xor_all_f(a : std_ulogic_vector) return std_ulogic is
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function xor_all_f(a : std_ulogic_vector) return std_ulogic is
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variable tmp_v : std_ulogic;
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variable tmp_v : std_ulogic;
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begin
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begin
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tmp_v := a(a'low);
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tmp_v := a(a'low);
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if (a'low < a'high) then -- not null range?
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for i in a'low+1 to a'high loop
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for i in a'low+1 to a'high loop
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tmp_v := tmp_v xor a(i);
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tmp_v := tmp_v xor a(i);
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end loop; -- i
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end loop; -- i
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end if;
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return tmp_v;
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return tmp_v;
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end function xor_all_f;
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end function xor_all_f;
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-- Function: XNOR all bits ----------------------------------------------------------------
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-- Function: XNOR all bits ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
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variable tmp_v : std_ulogic;
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variable tmp_v : std_ulogic;
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begin
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begin
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tmp_v := a(a'low);
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tmp_v := a(a'low);
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if (a'low < a'high) then -- not null range?
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for i in a'low+1 to a'high loop
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for i in a'low+1 to a'high loop
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tmp_v := tmp_v xnor a(i);
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tmp_v := tmp_v xnor a(i);
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end loop; -- i
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end loop; -- i
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end if;
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return tmp_v;
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return tmp_v;
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end function xnor_all_f;
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end function xnor_all_f;
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-- Function: Convert to hex char ----------------------------------------------------------
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-- Function: Convert to hex char ----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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