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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants/Configuration ---------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant data_width_c : natural := 32; -- data width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040303"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040309"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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-- Architecture Configuration -------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant ispace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"00000000"; -- default instruction memory address space base address
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constant dspace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"80000000"; -- default data memory address space base address
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constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
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constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Internal Types -------------------------------------------------------------------------
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-- Internal Types -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
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type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
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type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
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type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
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-- General Address Space Layout -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant ispace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"00000000"; -- default instruction memory space base address
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constant dspace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"80000000"; -- default data memory space base address
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-- Processor-Internal Address Space Layout ------------------------------------------------
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-- Processor-Internal Address Space Layout ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Internal Instruction Memory (IMEM) --
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-- Internal Instruction Memory (IMEM) --
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constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
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constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
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--> size is configured via top's generic
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--> size is configured via top's generic
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constant ctrl_rf_r0_we_c : natural := 18; -- allow write access to r0 (zero), also forces dst=r0
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constant ctrl_rf_r0_we_c : natural := 18; -- allow write access to r0 (zero), also forces dst=r0
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-- alu --
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-- alu --
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constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0
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constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0
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constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1
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constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1
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constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2
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constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2
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constant ctrl_alu_opa_mux_lsb_c : natural := 22; -- operand A select lsb (00=rs1, 01=PC)
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constant ctrl_alu_opa_mux_c : natural := 22; -- operand A select (0=rs1, 1=PC)
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constant ctrl_alu_opa_mux_msb_c : natural := 23; -- operand A select msb (1-=CSR)
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constant ctrl_alu_opb_mux_c : natural := 23; -- operand B select (0=rs2, 1=IMM)
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constant ctrl_alu_opb_mux_c : natural := 24; -- operand B select (0=rs2, 1=IMM)
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constant ctrl_alu_opc_mux_c : natural := 24; -- operand C select (0=rs2, 1=IMM)
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constant ctrl_alu_opc_mux_c : natural := 25; -- operand C select (0=rs2, 1=IMM)
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constant ctrl_alu_unsigned_c : natural := 25; -- is unsigned ALU operation
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constant ctrl_alu_unsigned_c : natural := 26; -- is unsigned ALU operation
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constant ctrl_alu_shift_dir_c : natural := 26; -- shift direction (0=left, 1=right)
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constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
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constant ctrl_alu_shift_ar_c : natural := 27; -- is arithmetic shift
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constant ctrl_alu_shift_ar_c : natural := 28; -- is arithmetic shift
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-- bus interface --
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-- bus interface --
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constant ctrl_bus_size_lsb_c : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
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constant ctrl_bus_size_lsb_c : natural := 28; -- transfer size lsb (00=byte, 01=half-word)
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constant ctrl_bus_size_msb_c : natural := 30; -- transfer size msb (10=word, 11=?)
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constant ctrl_bus_size_msb_c : natural := 29; -- transfer size msb (10=word, 11=?)
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constant ctrl_bus_rd_c : natural := 31; -- read data request
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constant ctrl_bus_rd_c : natural := 30; -- read data request
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constant ctrl_bus_wr_c : natural := 32; -- write data request
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constant ctrl_bus_wr_c : natural := 31; -- write data request
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constant ctrl_bus_if_c : natural := 33; -- instruction fetch request
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constant ctrl_bus_if_c : natural := 32; -- instruction fetch request
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constant ctrl_bus_mar_we_c : natural := 34; -- memory address register write enable
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constant ctrl_bus_mar_we_c : natural := 33; -- memory address register write enable
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constant ctrl_bus_mdo_we_c : natural := 35; -- memory data out register write enable
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constant ctrl_bus_mdo_we_c : natural := 34; -- memory data out register write enable
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constant ctrl_bus_mdi_we_c : natural := 36; -- memory data in register write enable
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constant ctrl_bus_mdi_we_c : natural := 35; -- memory data in register write enable
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constant ctrl_bus_unsigned_c : natural := 37; -- is unsigned load
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constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load
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constant ctrl_bus_ierr_ack_c : natural := 38; -- acknowledge instruction fetch bus exceptions
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constant ctrl_bus_ierr_ack_c : natural := 37; -- acknowledge instruction fetch bus exceptions
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constant ctrl_bus_derr_ack_c : natural := 39; -- acknowledge data access bus exceptions
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constant ctrl_bus_derr_ack_c : natural := 38; -- acknowledge data access bus exceptions
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constant ctrl_bus_fence_c : natural := 40; -- executed fence operation
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constant ctrl_bus_fence_c : natural := 39; -- executed fence operation
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constant ctrl_bus_fencei_c : natural := 41; -- executed fencei operation
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constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation
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-- co-processors --
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-- co-processors --
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constant ctrl_cp_use_c : natural := 42; -- is cp operation
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constant ctrl_cp_use_c : natural := 41; -- is cp operation
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constant ctrl_cp_id_lsb_c : natural := 43; -- cp select ID lsb
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constant ctrl_cp_id_lsb_c : natural := 42; -- cp select ID lsb
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constant ctrl_cp_id_msb_c : natural := 44; -- cp select ID msb
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constant ctrl_cp_id_msb_c : natural := 43; -- cp select ID msb
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constant ctrl_cp_cmd0_c : natural := 45; -- cp command bit 0
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constant ctrl_cp_cmd0_c : natural := 44; -- cp command bit 0
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constant ctrl_cp_cmd1_c : natural := 46; -- cp command bit 1
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constant ctrl_cp_cmd1_c : natural := 45; -- cp command bit 1
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constant ctrl_cp_cmd2_c : natural := 47; -- cp command bit 2
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constant ctrl_cp_cmd2_c : natural := 46; -- cp command bit 2
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-- control bus size --
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-- control bus size --
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constant ctrl_width_c : natural := 48; -- control bus size
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constant ctrl_width_c : natural := 47; -- control bus size
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constant ctrl_alu_aopb_inv_c : natural := 48;
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant alu_cmp_equal_c : natural := 0;
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constant alu_cmp_equal_c : natural := 0;
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constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
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constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
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constant alu_cmd_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- r <= A < B
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constant alu_cmd_slt_c : std_ulogic_vector(2 downto 0) := "010"; -- r <= A < B
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constant alu_cmd_shift_c : std_ulogic_vector(2 downto 0) := "011"; -- r <= A <</>> B
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constant alu_cmd_shift_c : std_ulogic_vector(2 downto 0) := "011"; -- r <= A <</>> B
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constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= A xor B
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constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= A xor B
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constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A or B
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constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A or B
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constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
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constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
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constant alu_cmd_bclr_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
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constant alu_cmd_movb_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= B
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-- Trap ID Codes --------------------------------------------------------------------------
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-- Trap ID Codes --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- risc-v compliant --
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-- risc-v compliant --
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constant trap_ima_c : std_ulogic_vector(5 downto 0) := "000000"; -- 0.0: instruction misaligned
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constant trap_ima_c : std_ulogic_vector(5 downto 0) := "000000"; -- 0.0: instruction misaligned
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bus_d_wait_i : in std_ulogic; -- wait for bus
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bus_d_wait_i : in std_ulogic; -- wait for bus
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-- data input --
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-- data input --
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
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alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU processing result
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-- data output --
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-- data output --
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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-- csr interface --
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic; -- machine software interrupt
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msw_irq_i : in std_ulogic; -- machine software interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- OPA + OPB
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- co-processor interface --
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-- co-processor interface --
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cp_opa_o : out std_ulogic_vector(data_width_c-1 downto 0); -- co-processor operand a
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cp_opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- co-processor operand b
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cp0_start_o : out std_ulogic; -- trigger co-processor 0
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cp0_start_o : out std_ulogic; -- trigger co-processor 0
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
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cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
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cp1_start_o : out std_ulogic; -- trigger co-processor 1
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cp1_start_o : out std_ulogic; -- trigger co-processor 1
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cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
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cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
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