| Line 53... |
Line 53... |
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
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constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
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-- Architecture Constants (do not modify!)= -----------------------------------------------
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-- Architecture Constants (do not modify!)= -----------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - do not change!
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constant data_width_c : natural := 32; -- data width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050000"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050003"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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| Line 706... |
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constant hpmcnt_event_never_c : natural := 1;
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constant hpmcnt_event_never_c : natural := 1;
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constant hpmcnt_event_ir_c : natural := 2; -- Retired instruction
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constant hpmcnt_event_ir_c : natural := 2; -- Retired instruction
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constant hpmcnt_event_cir_c : natural := 3; -- Retired compressed instruction
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constant hpmcnt_event_cir_c : natural := 3; -- Retired compressed instruction
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constant hpmcnt_event_wait_if_c : natural := 4; -- Instruction fetch memory wait cycle
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constant hpmcnt_event_wait_if_c : natural := 4; -- Instruction fetch memory wait cycle
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constant hpmcnt_event_wait_ii_c : natural := 5; -- Instruction issue wait cycle
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constant hpmcnt_event_wait_ii_c : natural := 5; -- Instruction issue wait cycle
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constant hpmcnt_event_load_c : natural := 6; -- Load operation
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constant hpmcnt_event_wait_mc_c : natural := 6; -- Multi-cycle ALU-operation wait cycle
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constant hpmcnt_event_store_c : natural := 7; -- Store operation
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constant hpmcnt_event_load_c : natural := 7; -- Load operation
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constant hpmcnt_event_wait_ls_c : natural := 8; -- Load/store memory wait cycle
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constant hpmcnt_event_store_c : natural := 8; -- Store operation
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constant hpmcnt_event_jump_c : natural := 9; -- Unconditional jump
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constant hpmcnt_event_wait_ls_c : natural := 9; -- Load/store memory wait cycle
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constant hpmcnt_event_branch_c : natural := 10; -- Conditional branch (taken or not taken)
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constant hpmcnt_event_jump_c : natural := 10; -- Unconditional jump
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constant hpmcnt_event_tbranch_c : natural := 11; -- Conditional taken branch
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constant hpmcnt_event_branch_c : natural := 11; -- Conditional branch (taken or not taken)
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constant hpmcnt_event_trap_c : natural := 12; -- Entered trap
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constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
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constant hpmcnt_event_illegal_c : natural := 13; -- Illegal instruction exception
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constant hpmcnt_event_trap_c : natural := 13; -- Entered trap
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constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
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--
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--
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constant hpmcnt_event_size_c : natural := 14; -- length of this list
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constant hpmcnt_event_size_c : natural := 15; -- length of this list
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-- Clock Generator ------------------------------------------------------------------------
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-- Clock Generator ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant clk_div2_c : natural := 0;
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constant clk_div2_c : natural := 0;
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constant clk_div4_c : natural := 1;
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constant clk_div4_c : natural := 1;
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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-- Internal Cache memory --
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-- Internal Cache memory --
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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-- External memory interface --
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-- External memory interface --
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MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
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MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
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IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
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d_bus_fence_o : out std_ulogic; -- fence operation
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d_bus_fence_o : out std_ulogic; -- fence operation
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d_bus_lock_o : out std_ulogic -- locked/exclusive access
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d_bus_lock_o : out std_ulogic -- locked/exclusive access
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);
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);
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end component;
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end component;
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-- Component: CPU Cache -------------------------------------------------------------------
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-- Component: CPU Instruction Cache -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cache
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component neorv32_icache
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generic (
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generic (
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CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2
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CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2
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CACHE_BLOCK_SIZE : natural := 16 -- block size in bytes (min 4), has to be a power of 2
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CACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
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CACHE_NUM_SETS : natural := 1 -- associativity / number of sets (1=direct_mapped), has to be a power of 2
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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