| Line 50... |
Line 50... |
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
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constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
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|
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-- CPU core --
|
-- CPU core --
|
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
|
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
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|
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-- "critical" number of PMP regions --
|
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-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically
|
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-- inserted into the memory interfaces increasing instruction fetch & data access latency by +1 cycle!
|
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constant pmp_num_regions_critical_c : natural := 8;
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|
|
-- Architecture Constants (do not modify!)= -----------------------------------------------
|
-- Architecture Constants (do not modify!)= -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- data width - do not change!
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050003"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050009"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
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|
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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| Line 88... |
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constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
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constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
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--> internal data/instruction memory sizes are configured via top's generics
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--> internal data/instruction memory sizes are configured via top's generics
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|
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-- Internal Bootloader ROM --
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-- Internal Bootloader ROM --
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constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
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constant boot_rom_size_c : natural := 4*1024; -- bytes
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constant boot_rom_size_c : natural := 4*1024; -- module's address space in bytes
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constant boot_rom_max_size_c : natural := 32*1024; -- bytes, fixed!
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constant boot_rom_max_size_c : natural := 32*1024; -- max module's address space in bytes, fixed!
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|
|
-- IO: Peripheral Devices ("IO") Area --
|
-- IO: Peripheral Devices ("IO") Area --
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-- Control register(s) (including the device-enable) should be located at the base address of each device
|
-- Control register(s) (including the device-enable) should be located at the base address of each device
|
constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
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constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
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constant io_size_c : natural := 32*4; -- bytes, fixed!
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constant io_size_c : natural := 64*4; -- module's address space in bytes, fixed!
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|
|
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-- Custom Functions Subsystem (CFS) --
|
|
constant cfs_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; -- base address
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constant cfs_size_c : natural := 32*4; -- module's address space in bytes
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constant cfs_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00";
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constant cfs_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF04";
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constant cfs_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF08";
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constant cfs_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF0C";
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constant cfs_reg4_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF10";
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constant cfs_reg5_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF14";
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constant cfs_reg6_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF18";
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constant cfs_reg7_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF1C";
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constant cfs_reg8_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF20";
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constant cfs_reg9_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF24";
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constant cfs_reg10_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF28";
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constant cfs_reg11_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF2C";
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constant cfs_reg12_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF30";
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constant cfs_reg13_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF34";
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constant cfs_reg14_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF38";
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constant cfs_reg15_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF3C";
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constant cfs_reg16_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF40";
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constant cfs_reg17_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF44";
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constant cfs_reg18_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF48";
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constant cfs_reg19_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF4C";
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constant cfs_reg20_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF50";
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constant cfs_reg21_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF54";
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constant cfs_reg22_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF58";
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constant cfs_reg23_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF5C";
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constant cfs_reg24_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF60";
|
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constant cfs_reg25_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF64";
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constant cfs_reg26_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF68";
|
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constant cfs_reg27_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF6C";
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constant cfs_reg28_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF70";
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constant cfs_reg29_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF74";
|
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constant cfs_reg30_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF78";
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constant cfs_reg31_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF7C";
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|
|
-- General Purpose Input/Output Unit (GPIO) --
|
-- General Purpose Input/Output Unit (GPIO) --
|
constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed!
|
constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address
|
constant gpio_size_c : natural := 2*4; -- bytes
|
constant gpio_size_c : natural := 2*4; -- module's address space in bytes
|
constant gpio_in_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
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constant gpio_in_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80";
|
constant gpio_out_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
|
constant gpio_out_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84";
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|
|
-- True Random Number Generator (TRNG) --
|
-- True Random Number Generator (TRNG) --
|
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed!
|
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address
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constant trng_size_c : natural := 1*4; -- bytes
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constant trng_size_c : natural := 1*4; -- module's address space in bytes
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constant trng_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
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constant trng_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88";
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|
|
-- Watch Dog Timer (WDT) --
|
-- Watch Dog Timer (WDT) --
|
constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed!
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constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address
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constant wdt_size_c : natural := 1*4; -- bytes
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constant wdt_size_c : natural := 1*4; -- module's address space in bytes
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constant wdt_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
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constant wdt_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C";
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|
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-- Machine System Timer (MTIME) --
|
-- Machine System Timer (MTIME) --
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constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address, fixed!
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constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address
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constant mtime_size_c : natural := 4*4; -- bytes
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constant mtime_size_c : natural := 4*4; -- module's address space in bytes
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constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
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constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
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constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
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constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
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constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
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constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
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constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
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constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
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|
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-- Universal Asynchronous Receiver/Transmitter (UART) --
|
-- Universal Asynchronous Receiver/Transmitter (UART) --
|
constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address, fixed!
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constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
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constant uart_size_c : natural := 2*4; -- bytes
|
constant uart_size_c : natural := 2*4; -- module's address space in bytes
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constant uart_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
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constant uart_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
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constant uart_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
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constant uart_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
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|
|
-- Serial Peripheral Interface (SPI) --
|
-- Serial Peripheral Interface (SPI) --
|
constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address, fixed!
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constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
|
constant spi_size_c : natural := 2*4; -- bytes
|
constant spi_size_c : natural := 2*4; -- module's address space in bytes
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constant spi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
|
constant spi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
|
constant spi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";
|
constant spi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC";
|
|
|
-- Two Wire Interface (TWI) --
|
-- Two Wire Interface (TWI) --
|
constant twi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address, fixed!
|
constant twi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address
|
constant twi_size_c : natural := 2*4; -- bytes
|
constant twi_size_c : natural := 2*4; -- module's address space in bytes
|
constant twi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";
|
constant twi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0";
|
constant twi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";
|
constant twi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4";
|
|
|
-- Pulse-Width Modulation Controller (PWM) --
|
-- Pulse-Width Modulation Controller (PWM) --
|
constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed!
|
constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address
|
constant pwm_size_c : natural := 2*4; -- bytes
|
constant pwm_size_c : natural := 2*4; -- module's address space in bytes
|
constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
|
constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8";
|
constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
|
constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC";
|
|
|
-- Custom Functions Unit 0 (CFU0) --
|
-- reserved --
|
constant cfu0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
|
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address
|
constant cfu0_size_c : natural := 4*4; -- bytes
|
--constant reserved_size_c : natural := 8*4; -- module's address space in bytes
|
constant cfu0_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
|
|
constant cfu0_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
|
|
constant cfu0_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
|
|
constant cfu0_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
|
|
|
|
-- Custom Functions Unit 1 (CFU1) --
|
|
constant cfu1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed!
|
|
constant cfu1_size_c : natural := 4*4; -- bytes
|
|
constant cfu1_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
|
|
constant cfu1_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
|
|
constant cfu1_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8";
|
|
constant cfu1_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC";
|
|
|
|
-- System Information Memory (SYSINFO) --
|
-- System Information Memory (SYSINFO) --
|
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
|
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
|
constant sysinfo_size_c : natural := 8*4; -- bytes
|
constant sysinfo_size_c : natural := 8*4; -- module's address space in bytes
|
|
|
-- Main Control Bus -----------------------------------------------------------------------
|
-- Main Control Bus -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- register file --
|
-- register file --
|
constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (10=MEM, 11=CSR)
|
constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (10=MEM, 11=CSR)
|
| Line 241... |
Line 270... |
constant ctrl_ir_opcode7_2_c : natural := 64; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_2_c : natural := 64; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_3_c : natural := 65; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6
|
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6
|
|
-- CPU status --
|
|
constant ctrl_sleep_c : natural := 69; -- set when CPU is in sleep mode
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 69; -- control bus size
|
constant ctrl_width_c : natural := 70; -- control bus size
|
|
|
-- ALU Comparator Bus ---------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant alu_cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
|
|
-- RISC-V Opcode Layout -------------------------------------------------------------------
|
-- RISC-V Opcode Layout -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
|
constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
|
constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
|
constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
|
| Line 666... |
Line 697... |
constant trap_reset_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0: hardware reset
|
constant trap_reset_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0: hardware reset
|
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
|
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
|
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
|
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
|
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
|
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
|
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
|
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
|
|
constant trap_firq4_c : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
|
|
constant trap_firq5_c : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
|
|
constant trap_firq6_c : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
|
|
constant trap_firq7_c : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
|
|
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- exception source bits --
|
-- exception source bits --
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
| Line 690... |
Line 725... |
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
|
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
|
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
|
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
|
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
|
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
|
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
|
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
|
|
constant interrupt_firq_4_c : natural := 7; -- fast interrupt channel 4
|
|
constant interrupt_firq_5_c : natural := 8; -- fast interrupt channel 5
|
|
constant interrupt_firq_6_c : natural := 9; -- fast interrupt channel 6
|
|
constant interrupt_firq_7_c : natural := 10; -- fast interrupt channel 7
|
--
|
--
|
constant interrupt_width_c : natural := 7; -- length of this list in bits
|
constant interrupt_width_c : natural := 11; -- length of this list in bits
|
|
|
-- CPU Privilege Modes --------------------------------------------------------------------
|
-- CPU Privilege Modes --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
|
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
|
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
|
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
|
| Line 754... |
Line 793... |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29)
|
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
-- Internal Instruction memory --
|
-- Internal Instruction memory --
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
-- Internal Data memory --
|
-- Internal Data memory --
|
| Line 778... |
Line 817... |
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
IO_CFU0_EN : boolean := false; -- implement custom functions unit 0 (CFU0)?
|
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
|
IO_CFU1_EN : boolean := false -- implement custom functions unit 1 (CFU1)?
|
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 816... |
Line 855... |
-- TWI --
|
-- TWI --
|
twi_sda_io : inout std_logic; -- twi serial data line
|
twi_sda_io : inout std_logic; -- twi serial data line
|
twi_scl_io : inout std_logic; -- twi serial clock line
|
twi_scl_io : inout std_logic; -- twi serial clock line
|
-- PWM --
|
-- PWM --
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
|
-- Custom Functions Subsystem IO --
|
|
cfs_in_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CSF inputs
|
|
cfs_out_o : out std_ulogic_vector(31 downto 0); -- custom CSF outputs
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
-- Interrupts --
|
-- Interrupts --
|
|
soc_firq_i : in std_ulogic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
);
|
);
|
end component;
|
end component;
|
| Line 849... |
Line 892... |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29)
|
HPM_NUM_CNTS : natural := 0 -- number of implemented HPM counters (0..29)
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
|
-- instruction bus interface --
|
-- instruction bus interface --
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 888... |
Line 932... |
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
|
firq_i : in std_ulogic_vector(7 downto 0) := (others => '0');
|
|
firq_ack_o : out std_ulogic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 912... |
Line 957... |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Hardware Performance Monitors (HPM) --
|
-- Hardware Performance Monitors (HPM) --
|
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29)
|
HPM_NUM_CNTS : natural := 0 -- number of implemented HPM counters (0..29)
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 938... |
Line 983... |
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i : in std_ulogic_vector(3 downto 0);
|
firq_i : in std_ulogic_vector(7 downto 0);
|
|
firq_ack_o : out std_ulogic_vector(7 downto 0);
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- physical memory protection --
|
-- physical memory protection --
|
pmp_addr_o : out pmp_addr_if_t; -- addresses
|
pmp_addr_o : out pmp_addr_if_t; -- addresses
|
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
|
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
|
| Line 971... |
Line 1017... |
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
-- data output --
|
-- data output --
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
|
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
|
|
cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 993... |
Line 1040... |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
|
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
|
-- data output --
|
-- data output --
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
|
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
|
-- co-processor interface --
|
-- co-processor interface --
|
cp0_start_o : out std_ulogic; -- trigger co-processor 0
|
cp0_start_o : out std_ulogic; -- trigger co-processor 0
|
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
|
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
|
| Line 1122... |
Line 1168... |
|
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- Component: CPU Instruction Cache -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_icache
|
component neorv32_icache
|
generic (
|
generic (
|
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2
|
ICACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2
|
CACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
|
ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
|
CACHE_NUM_SETS : natural := 1 -- associativity / number of sets (1=direct_mapped), has to be a power of 2
|
ICACHE_NUM_SETS : natural := 1 -- associativity / number of sets (1=direct_mapped), has to be a power of 2
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 1484... |
Line 1530... |
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_ack_i : in std_ulogic; -- transfer acknowledge
|
wb_err_i : in std_ulogic -- transfer error
|
wb_err_i : in std_ulogic -- transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: Custom Functions Unit 0 (CFU0) ----------------------------------------------
|
-- Component: Custom Functions Subsystem (CFS) --------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cfu0
|
component neorv32_cfs
|
port (
|
generic (
|
-- host access --
|
CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic
|
clk_i : in std_ulogic; -- global clock line
|
|
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
rden_i : in std_ulogic; -- read enable
|
|
wren_i : in std_ulogic; -- write enable
|
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
|
ack_o : out std_ulogic; -- transfer acknowledge
|
|
-- clock generator --
|
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
|
clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs
|
|
-- custom io --
|
|
-- ...
|
|
);
|
);
|
end component;
|
|
|
|
-- Component: Custom Functions Unit 1 (CFU1) ----------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_cfu1
|
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
|
rstn_i : in std_ulogic; -- global reset line, low-active, use as async
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- word write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
|
err_o : out std_ulogic; -- transfer error
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs
|
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
|
-- custom io --
|
-- CPU state --
|
-- ...
|
sleep_i : in std_ulogic; -- set if cpu is in sleep mode
|
|
-- interrupt --
|
|
irq_o : out std_ulogic; -- interrupt request
|
|
irq_ack_i : in std_ulogic; -- interrupt acknowledge
|
|
-- custom io (conduit) --
|
|
cfs_in_i : in std_ulogic_vector(31 downto 0); -- custom inputs
|
|
cfs_out_o : out std_ulogic_vector(31 downto 0) -- custom outputs
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
-- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 1557... |
Line 1592... |
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
|
IO_CFU0_EN : boolean := true; -- implement custom functions unit 0 (CFU0)?
|
IO_CFS_EN : boolean := true -- implement custom functions subsystem (CFS)?
|
IO_CFU1_EN : boolean := true -- implement custom functions unit 1 (CFU1)?
|
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
