| Line 58... |
Line 58... |
constant pmp_num_regions_critical_c : natural := 8;
|
constant pmp_num_regions_critical_c : natural := 8;
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050104"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050107"; -- no touchy!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
|
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
|
|
|
-- Helper Functions -----------------------------------------------------------------------
|
-- Helper Functions -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function index_size_f(input : natural) return natural;
|
function index_size_f(input : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
|
|
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic;
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic;
|
function or_all_f(a : std_ulogic_vector) return std_ulogic;
|
function or_all_f(a : std_ulogic_vector) return std_ulogic;
|
function and_all_f(a : std_ulogic_vector) return std_ulogic;
|
function and_all_f(a : std_ulogic_vector) return std_ulogic;
|
function xor_all_f(a : std_ulogic_vector) return std_ulogic;
|
function xor_all_f(a : std_ulogic_vector) return std_ulogic;
|
function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
|
function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
|
| Line 162... |
Line 163... |
constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
|
constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90";
|
constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
|
constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94";
|
constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
|
constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98";
|
constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
|
constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C";
|
|
|
-- Universal Asynchronous Receiver/Transmitter (UART) --
|
-- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
|
constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
|
constant uart0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address
|
constant uart_size_c : natural := 2*4; -- module's address space in bytes
|
constant uart0_size_c : natural := 2*4; -- module's address space in bytes
|
constant uart_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
|
constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0";
|
constant uart_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
|
constant uart0_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4";
|
|
|
-- Serial Peripheral Interface (SPI) --
|
-- Serial Peripheral Interface (SPI) --
|
constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
|
constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address
|
constant spi_size_c : natural := 2*4; -- module's address space in bytes
|
constant spi_size_c : natural := 2*4; -- module's address space in bytes
|
constant spi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
|
constant spi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8";
|
| Line 194... |
Line 195... |
constant nco_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
|
constant nco_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0";
|
constant nco_ch0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
|
constant nco_ch0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4";
|
constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
|
constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8";
|
constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
|
constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC";
|
|
|
|
-- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
|
|
constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
|
|
constant uart1_size_c : natural := 2*4; -- module's address space in bytes
|
|
constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0";
|
|
constant uart1_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4";
|
|
|
-- reserved --
|
-- reserved --
|
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address
|
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8"; -- base address
|
--constant reserved_size_c : natural := 4*4; -- module's address space in bytes
|
--constant reserved_size_c : natural := 2*4; -- module's address space in bytes
|
|
|
-- System Information Memory (SYSINFO) --
|
-- System Information Memory (SYSINFO) --
|
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
|
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address
|
constant sysinfo_size_c : natural := 8*4; -- module's address space in bytes
|
constant sysinfo_size_c : natural := 8*4; -- module's address space in bytes
|
|
|
| Line 840... |
Line 847... |
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
| Line 872... |
Line 880... |
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
-- GPIO (available if IO_GPIO_EN = true) --
|
-- GPIO (available if IO_GPIO_EN = true) --
|
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
-- UART (available if IO_UART_EN = true) --
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart0_txd_o : out std_ulogic; -- UART0 send data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
|
|
-- secondary UART1 (available if IO_UART1_EN = true) --
|
|
uart1_txd_o : out std_ulogic; -- UART1 send data
|
|
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
|
-- SPI (available if IO_SPI_EN = true) --
|
-- SPI (available if IO_SPI_EN = true) --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
| Line 893... |
Line 904... |
-- NCO output (available if IO_NCO_EN = true) --
|
-- NCO output (available if IO_NCO_EN = true) --
|
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
|
nco_o : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
-- Interrupts --
|
-- Interrupts --
|
soc_firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); -- fast interrupt channels
|
soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
);
|
);
|
end component;
|
end component;
|
| Line 1405... |
Line 1416... |
end component;
|
end component;
|
|
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_uart
|
component neorv32_uart
|
|
generic (
|
|
UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
|
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
| Line 1569... |
Line 1583... |
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- word write enable
|
wren_i : in std_ulogic; -- word write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
err_o : out std_ulogic; -- transfer error
|
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
|
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
|
-- CPU state --
|
-- CPU state --
|
sleep_i : in std_ulogic; -- set if cpu is in sleep mode
|
sleep_i : in std_ulogic; -- set if cpu is in sleep mode
|
| Line 1629... |
Line 1642... |
-- External memory interface --
|
-- External memory interface --
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_EN : boolean := false; -- implement external memory bus interface?
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART_EN : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)?
|
| Line 1686... |
Line 1700... |
else
|
else
|
return val_f;
|
return val_f;
|
end if;
|
end if;
|
end function cond_sel_stdulogicvector_f;
|
end function cond_sel_stdulogicvector_f;
|
|
|
-- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
|
-- Function: Conditional select string ----------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is
|
|
begin
|
|
if (cond = true) then
|
|
return val_t;
|
|
else
|
|
return val_f;
|
|
end if;
|
|
end function cond_sel_string_f;
|
|
|
|
-- Function: Convert bool to std_ulogic ---------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic is
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic is
|
begin
|
begin
|
if (cond = true) then
|
if (cond = true) then
|
return '1';
|
return '1';
|
