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constant pmp_num_regions_critical_c : natural := 8;
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constant pmp_num_regions_critical_c : natural := 8;
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-- Architecture Constants (do not modify!) ------------------------------------------------
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-- Architecture Constants (do not modify!) ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050107"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050200"; -- no touchy!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
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constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
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-- Helper Functions -----------------------------------------------------------------------
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-- Helper Functions -----------------------------------------------------------------------
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gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
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gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
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gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
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gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
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-- primary UART0 (available if IO_UART0_EN = true) --
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-- primary UART0 (available if IO_UART0_EN = true) --
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uart0_txd_o : out std_ulogic; -- UART0 send data
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uart0_txd_o : out std_ulogic; -- UART0 send data
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uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
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uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
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uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
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uart0_cts_i : in std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
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-- secondary UART1 (available if IO_UART1_EN = true) --
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-- secondary UART1 (available if IO_UART1_EN = true) --
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uart1_txd_o : out std_ulogic; -- UART1 send data
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uart1_txd_o : out std_ulogic; -- UART1 send data
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uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
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uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
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uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
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uart1_cts_i : in std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
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-- SPI (available if IO_SPI_EN = true) --
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-- SPI (available if IO_SPI_EN = true) --
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
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spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
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spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- com lines --
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-- com lines --
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uart_txd_o : out std_ulogic;
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uart_txd_o : out std_ulogic;
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uart_rxd_i : in std_ulogic;
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uart_rxd_i : in std_ulogic;
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-- hardware flow control --
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uart_rts_o : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
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uart_cts_i : in std_ulogic; -- UART.TX allowed to transmit, low-active, optional
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-- interrupts --
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-- interrupts --
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irq_rxd_o : out std_ulogic; -- uart data received interrupt
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irq_rxd_o : out std_ulogic; -- uart data received interrupt
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irq_txd_o : out std_ulogic -- uart transmission done interrupt
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irq_txd_o : out std_ulogic -- uart transmission done interrupt
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);
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);
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end component;
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end component;
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