| Line 81... |
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function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
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function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
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-- Architecture Constants (do not modify!) ------------------------------------------------
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-- Architecture Constants (do not modify!) ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050408"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050500"; -- no touchy!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
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constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
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constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
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constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
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constant def_rst_val_c : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
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-- Internal Types -------------------------------------------------------------------------
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-- Internal Types -------------------------------------------------------------------------
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constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";
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constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";
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constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff94";
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constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff94";
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constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";
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constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";
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constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";
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constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";
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-- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
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-- Primary Universal Asynchronous Receiver/Transmitter (UART0) --
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constant uart0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address
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constant uart0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address
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constant uart0_size_c : natural := 2*4; -- module's address space in bytes
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constant uart0_size_c : natural := 2*4; -- module's address space in bytes
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constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";
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constant uart0_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";
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constant uart0_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa4";
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constant uart0_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa4";
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constant nco_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0";
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constant nco_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0";
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constant nco_ch0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4";
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constant nco_ch0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4";
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constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
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constant nco_ch1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
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constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
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constant nco_ch2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
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-- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
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-- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --
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constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
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constant uart1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
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constant uart1_size_c : natural := 2*4; -- module's address space in bytes
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constant uart1_size_c : natural := 2*4; -- module's address space in bytes
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constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";
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constant uart1_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";
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constant uart1_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd4";
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constant uart1_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd4";
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| Line 231... |
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constant ctrl_rf_rs2_adr0_c : natural := 6; -- source register 2 address bit 0
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constant ctrl_rf_rs2_adr0_c : natural := 6; -- source register 2 address bit 0
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constant ctrl_rf_rs2_adr1_c : natural := 7; -- source register 2 address bit 1
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constant ctrl_rf_rs2_adr1_c : natural := 7; -- source register 2 address bit 1
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constant ctrl_rf_rs2_adr2_c : natural := 8; -- source register 2 address bit 2
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constant ctrl_rf_rs2_adr2_c : natural := 8; -- source register 2 address bit 2
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constant ctrl_rf_rs2_adr3_c : natural := 9; -- source register 2 address bit 3
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constant ctrl_rf_rs2_adr3_c : natural := 9; -- source register 2 address bit 3
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constant ctrl_rf_rs2_adr4_c : natural := 10; -- source register 2 address bit 4
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constant ctrl_rf_rs2_adr4_c : natural := 10; -- source register 2 address bit 4
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constant ctrl_rf_rd_adr0_c : natural := 11; -- destiantion register address bit 0
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constant ctrl_rf_rd_adr0_c : natural := 11; -- destination register address bit 0
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constant ctrl_rf_rd_adr1_c : natural := 12; -- destiantion register address bit 1
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constant ctrl_rf_rd_adr1_c : natural := 12; -- destination register address bit 1
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constant ctrl_rf_rd_adr2_c : natural := 13; -- destiantion register address bit 2
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constant ctrl_rf_rd_adr2_c : natural := 13; -- destination register address bit 2
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constant ctrl_rf_rd_adr3_c : natural := 14; -- destiantion register address bit 3
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constant ctrl_rf_rd_adr3_c : natural := 14; -- destination register address bit 3
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constant ctrl_rf_rd_adr4_c : natural := 15; -- destiantion register address bit 4
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constant ctrl_rf_rd_adr4_c : natural := 15; -- destination register address bit 4
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constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
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constant ctrl_rf_wb_en_c : natural := 16; -- write back enable
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constant ctrl_rf_r0_we_c : natural := 17; -- force write access and force rd=r0
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constant ctrl_rf_r0_we_c : natural := 17; -- force write access and force rd=r0
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-- alu --
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-- alu --
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constant ctrl_alu_arith_c : natural := 18; -- ALU arithmetic command
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constant ctrl_alu_arith_c : natural := 18; -- ALU arithmetic command
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constant ctrl_alu_logic0_c : natural := 19; -- ALU logic command bit 0
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constant ctrl_alu_logic0_c : natural := 19; -- ALU logic command bit 0
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constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb";
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constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb";
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constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec";
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constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec";
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constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
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constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
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constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
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constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
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constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
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constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
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---- debug mode registers --
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--constant csr_class_debug_c : std_ulogic_vector(09 downto 0) := x"7b" & "00"; -- debug registers
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--constant csr_dcsr_c : std_ulogic_vector(11 downto 0) := x"7b0";
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--constant csr_dpc_c : std_ulogic_vector(11 downto 0) := x"7b1";
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--constant csr_dsratch0_c : std_ulogic_vector(11 downto 0) := x"7b2";
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--constant csr_dsratch1_c : std_ulogic_vector(11 downto 0) := x"7b3";
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-- machine counters/timers --
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-- machine counters/timers --
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constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00";
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constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00";
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constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02";
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constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02";
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--
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--
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constant csr_mhpmcounter3_c : std_ulogic_vector(11 downto 0) := x"b03";
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constant csr_mhpmcounter3_c : std_ulogic_vector(11 downto 0) := x"b03";
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constant trap_sma_c : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6: store address misaligned
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constant trap_sma_c : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6: store address misaligned
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constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7: store access fault
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constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7: store access fault
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constant trap_uenv_c : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8: environment call from u-mode
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constant trap_uenv_c : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8: environment call from u-mode
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constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
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constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
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-- RISC-V compliant interrupts (async. exceptions) --
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-- RISC-V compliant interrupts (async. exceptions) --
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constant trap_nmi_c : std_ulogic_vector(5 downto 0) := "1" & "00000"; -- 1.0: non-maskable interrupt
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constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt
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constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt
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constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt
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constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt
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constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
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constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
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-- NEORV32-specific (custom) interrupts (async. exceptions) --
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-- NEORV32-specific (custom) interrupts (async. exceptions) --
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constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
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constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
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| Line 801... |
Line 808... |
constant exception_saccess_c : natural := 8; -- store access fault
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constant exception_saccess_c : natural := 8; -- store access fault
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constant exception_laccess_c : natural := 9; -- load access fault
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constant exception_laccess_c : natural := 9; -- load access fault
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--
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--
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constant exception_width_c : natural := 10; -- length of this list in bits
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constant exception_width_c : natural := 10; -- length of this list in bits
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-- interrupt source bits --
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-- interrupt source bits --
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constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
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constant interrupt_nm_irq_c : natural := 0; -- non-maskable interrupt
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constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
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constant interrupt_msw_irq_c : natural := 1; -- machine software interrupt
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constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
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constant interrupt_mtime_irq_c : natural := 2; -- machine timer interrupt
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constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0
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constant interrupt_mext_irq_c : natural := 3; -- machine external interrupt
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constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1
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constant interrupt_firq_0_c : natural := 4; -- fast interrupt channel 0
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constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2
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constant interrupt_firq_1_c : natural := 5; -- fast interrupt channel 1
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constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3
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constant interrupt_firq_2_c : natural := 6; -- fast interrupt channel 2
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constant interrupt_firq_4_c : natural := 7; -- fast interrupt channel 4
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constant interrupt_firq_3_c : natural := 7; -- fast interrupt channel 3
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constant interrupt_firq_5_c : natural := 8; -- fast interrupt channel 5
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constant interrupt_firq_4_c : natural := 8; -- fast interrupt channel 4
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constant interrupt_firq_6_c : natural := 9; -- fast interrupt channel 6
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constant interrupt_firq_5_c : natural := 9; -- fast interrupt channel 5
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constant interrupt_firq_7_c : natural := 10; -- fast interrupt channel 7
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constant interrupt_firq_6_c : natural := 10; -- fast interrupt channel 6
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constant interrupt_firq_8_c : natural := 11; -- fast interrupt channel 8
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constant interrupt_firq_7_c : natural := 11; -- fast interrupt channel 7
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constant interrupt_firq_9_c : natural := 12; -- fast interrupt channel 9
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constant interrupt_firq_8_c : natural := 12; -- fast interrupt channel 8
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constant interrupt_firq_10_c : natural := 13; -- fast interrupt channel 10
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constant interrupt_firq_9_c : natural := 13; -- fast interrupt channel 9
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constant interrupt_firq_11_c : natural := 14; -- fast interrupt channel 11
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constant interrupt_firq_10_c : natural := 14; -- fast interrupt channel 10
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constant interrupt_firq_12_c : natural := 15; -- fast interrupt channel 12
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constant interrupt_firq_11_c : natural := 15; -- fast interrupt channel 11
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constant interrupt_firq_13_c : natural := 16; -- fast interrupt channel 13
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constant interrupt_firq_12_c : natural := 16; -- fast interrupt channel 12
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constant interrupt_firq_14_c : natural := 17; -- fast interrupt channel 14
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constant interrupt_firq_13_c : natural := 17; -- fast interrupt channel 13
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constant interrupt_firq_15_c : natural := 18; -- fast interrupt channel 15
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constant interrupt_firq_14_c : natural := 18; -- fast interrupt channel 14
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constant interrupt_firq_15_c : natural := 19; -- fast interrupt channel 15
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--
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--
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constant interrupt_width_c : natural := 19; -- length of this list in bits
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constant interrupt_width_c : natural := 20; -- length of this list in bits
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-- CPU Privilege Modes --------------------------------------------------------------------
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-- CPU Privilege Modes --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
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constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
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constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
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constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
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| Line 973... |
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
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neoled_o : out std_ulogic; -- async serial data line
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neoled_o : out std_ulogic; -- async serial data line
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-- system time input from external MTIME (available if IO_MTIME_EN = false) --
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-- system time input from external MTIME (available if IO_MTIME_EN = false) --
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mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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-- Interrupts --
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-- Interrupts --
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nm_irq_i : in std_ulogic := '0'; -- non-maskable interrupt
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soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
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soc_firq_i : in std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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mext_irq_i : in std_ulogic := '0' -- machine external interrupt
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mext_irq_i : in std_ulogic := '0' -- machine external interrupt
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);
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);
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| Line 1040... |
Line 1049... |
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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-- non-maskable interrupt --
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nm_irq_i : in std_ulogic := '0'; -- NMI
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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| Line 1099... |
Line 1110... |
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- FPU interface --
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-- FPU interface --
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fpu_rm_o : out std_ulogic_vector(02 downto 0); -- rounding mode
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fpu_rm_o : out std_ulogic_vector(02 downto 0); -- rounding mode
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fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
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fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
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-- non-maskable interrupt --
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nm_irq_i : in std_ulogic;
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic; -- machine software interrupt
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msw_irq_i : in std_ulogic; -- machine software interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mext_irq_i : in std_ulogic; -- machine external interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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