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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"00000206"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000000"; -- no touchy!
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-- Internal Functions ---------------------------------------------------------------------
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-- Internal Functions ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function index_size_f(input : natural) return natural;
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function index_size_f(input : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function bool_to_ulogic_f(cond : boolean) return std_ulogic;
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function bool_to_ulogic_f(cond : boolean) return std_ulogic;
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function or_all_f( a : std_ulogic_vector) return std_ulogic;
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function or_all_f( a : std_ulogic_vector) return std_ulogic;
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function and_all_f( a : std_ulogic_vector) return std_ulogic;
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function and_all_f( a : std_ulogic_vector) return std_ulogic;
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function xor_all_f( a : std_ulogic_vector) return std_ulogic;
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function xor_all_f( a : std_ulogic_vector) return std_ulogic;
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
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function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
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function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
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-- Processor-internal Address Space Layout ------------------------------------------------
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-- Processor-internal Address Space Layout ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Instruction Memory & Data Memory --
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-- Instruction Memory & Data Memory --
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-- => configured via top's generics
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-- => configured via top's generics
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-- alu --
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-- alu --
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constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
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constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
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constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
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constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
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constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
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constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
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constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
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constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
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constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (10=CSR, 11=CSR)
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constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (10=CSR, 11=?)
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constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=PC)
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constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM)
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constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (10=rs1, 11=PC_increment(2/4))
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constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (10=rs1, 11=?)
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constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
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constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
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constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
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constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
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constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
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constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
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constant ctrl_alu_shift_ar_c : natural := 30; -- is arithmetic shift
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constant ctrl_alu_shift_ar_c : natural := 30; -- is arithmetic shift
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-- bus interface --
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-- bus interface --
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constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
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constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
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constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
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constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
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constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
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constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
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constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
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constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
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constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
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constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
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-- csr/system --
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constant ctrl_csr_pc_we_c : natural := 40; -- PC write enable
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constant ctrl_csr_re_c : natural := 41; -- valid CSR read
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constant ctrl_csr_we_c : natural := 42; -- valid CSR write
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-- co-processor --
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-- co-processor --
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constant ctrl_cp_use_c : natural := 43; -- is cp operation
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constant ctrl_cp_use_c : natural := 40; -- is cp operation
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constant ctrl_cp_id_lsb_c : natural := 44; -- cp select lsb
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constant ctrl_cp_id_lsb_c : natural := 41; -- cp select lsb
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constant ctrl_cp_id_msb_c : natural := 45; -- cp select msb
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constant ctrl_cp_id_msb_c : natural := 42; -- cp select msb
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constant ctrl_cp_cmd0_c : natural := 46; -- cp command bit 0
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constant ctrl_cp_cmd0_c : natural := 43; -- cp command bit 0
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constant ctrl_cp_cmd1_c : natural := 47; -- cp command bit 1
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constant ctrl_cp_cmd1_c : natural := 44; -- cp command bit 1
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constant ctrl_cp_cmd2_c : natural := 48; -- cp command bit 2
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constant ctrl_cp_cmd2_c : natural := 45; -- cp command bit 2
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-- system --
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constant ctrl_sys_c_ext_en_c : natural := 46; -- CPU C extension enabled
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constant ctrl_sys_m_ext_en_c : natural := 47; -- CPU M extension enabled
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-- control bus size --
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-- control bus size --
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constant ctrl_width_c : natural := 49; -- control bus size
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constant ctrl_width_c : natural := 48; -- control bus size
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant alu_cmp_equal_c : natural := 0;
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constant alu_cmp_equal_c : natural := 0;
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constant alu_cmp_less_c : natural := 1; -- for signed and unsigned
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constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
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-- RISC-V Opcode Layout -------------------------------------------------------------------
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-- RISC-V Opcode Layout -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
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constant instr_opcode_lsb_c : natural := 0; -- opcode bit 0
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constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
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constant instr_opcode_msb_c : natural := 6; -- opcode bit 6
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generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
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gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
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-- UART --
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-- UART --
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uart_txd_o : out std_ulogic; -- UART send data
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uart_txd_o : out std_ulogic; -- UART send data
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uart_rxd_i : in std_ulogic := '0'; -- UART receive data
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uart_rxd_i : in std_ulogic := '0'; -- UART receive data
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-- SPI --
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-- SPI --
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spi_sclk_o : out std_ulogic; -- serial clock line
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_mosi_o : out std_ulogic; -- serial data line out
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
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spi_miso_i : in std_ulogic := '0'; -- serial data line in
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spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
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-- TWI --
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-- TWI --
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twi_sda_io : inout std_logic := 'H'; -- twi serial data line
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twi_sda_io : inout std_logic := 'H'; -- twi serial data line
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twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
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twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
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-- PWM --
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-- PWM --
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generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
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alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
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-- data output --
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-- data output --
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC
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fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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alu_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC for ALU
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
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-- csr interface --
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-- csr interface --
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- external interrupt --
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-- external interrupt --
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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Line 533... |
ma_load_i : in std_ulogic; -- misaligned load data address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_store_i : in std_ulogic; -- bus error on store data access
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be_store_i : in std_ulogic; -- bus error on store data access
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bus_exc_ack_o : out std_ulogic -- bus exception error acknowledge
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bus_exc_ack_o : out std_ulogic; -- bus exception error acknowledge
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bus_busy_i : in std_ulogic -- bus unit is busy
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);
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);
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end component;
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end component;
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-- Component: CPU Register File -----------------------------------------------------------
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-- Component: CPU Register File -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 557... |
Line 562... |
end component;
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end component;
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-- Component: CPU ALU ---------------------------------------------------------------------
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-- Component: CPU ALU ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_alu
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component neorv32_cpu_alu
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generic (
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_M : boolean := false -- implement mul/div extension?
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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| Line 608... |
Line 608... |
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-- Component: CPU Bus Interface -----------------------------------------------------------
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-- Component: CPU Bus Interface -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_bus
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component neorv32_cpu_bus
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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| Line 632... |
Line 631... |
ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data
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be_store_o : out std_ulogic; -- bus error on store data
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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bus_busy_o : out std_ulogic; -- bus unit is busy
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exc_ack_i : in std_ulogic; -- exception controller ACK
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exc_ack_i : in std_ulogic; -- exception controller ACK
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-- bus system --
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-- bus system --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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| Line 652... |
Line 652... |
component neorv32_cpu_decompressor
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component neorv32_cpu_decompressor
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port (
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port (
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-- instruction input --
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-- instruction input --
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ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
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ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
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-- instruction output --
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-- instruction output --
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ci_valid_o : out std_ulogic; -- is a compressed instruction
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ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
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ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
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ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
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ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
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);
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);
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end component;
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end component;
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| Line 836... |
Line 835... |
ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- com lines --
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-- com lines --
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spi_sclk_o : out std_ulogic; -- SPI serial clock
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spi_sck_o : out std_ulogic; -- SPI serial clock
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spi_mosi_o : out std_ulogic; -- SPI master out, slave in
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spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_miso_i : in std_ulogic; -- SPI master in, slave out
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- interrupt --
|
-- interrupt --
|
spi_irq_o : out std_ulogic -- transmission done interrupt
|
spi_irq_o : out std_ulogic -- transmission done interrupt
|
);
|
);
|
end component;
|
end component;
|
| Line 1061... |
Line 1060... |
tmp_v := tmp_v xnor a(i);
|
tmp_v := tmp_v xnor a(i);
|
end loop; -- i
|
end loop; -- i
|
return tmp_v;
|
return tmp_v;
|
end function xnor_all_f;
|
end function xnor_all_f;
|
|
|
|
-- Function: Convert to hex char ----------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
|
|
variable output_v : character;
|
|
begin
|
|
case input is
|
|
when x"0" => output_v := '0';
|
|
when x"1" => output_v := '1';
|
|
when x"2" => output_v := '2';
|
|
when x"3" => output_v := '3';
|
|
when x"4" => output_v := '4';
|
|
when x"5" => output_v := '5';
|
|
when x"6" => output_v := '6';
|
|
when x"7" => output_v := '7';
|
|
when x"8" => output_v := '8';
|
|
when x"9" => output_v := '9';
|
|
when x"a" => output_v := 'a';
|
|
when x"b" => output_v := 'b';
|
|
when x"c" => output_v := 'c';
|
|
when x"d" => output_v := 'd';
|
|
when x"e" => output_v := 'e';
|
|
when x"f" => output_v := 'f';
|
|
when others => output_v := '?';
|
|
end case;
|
|
return output_v;
|
|
end function to_hexchar_f;
|
|
|
end neorv32_package;
|
end neorv32_package;
|
|
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No newline at end of file
|
